final: use default values

Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

flow/scripts/final_report.tcl

@@ -21,7 +21,7 @@ write_verilog $::env(RESULTS_DIR)/6_final.v \
 # Run extraction and STA
 if {
   [env_var_exists_and_non_empty RCX_RULES]
-  && [env_var_equals SKIP_DETAILED_ROUTE 0]
+  && !$::env(SKIP_DETAILED_ROUTE)
 } {
   # RCX section
   define_process_corner -ext_model_index 0 X