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2 parents d012f05 + d57a0c5 commit 8184f71Copy full SHA for 8184f71
flow/Makefile
@@ -377,7 +377,7 @@ ifeq ($(wildcard $(3)),)
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# each macro.
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block := $(patsubst ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/%,%,$(dir $(3)))
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$(1) $(2) &:
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- $$(UNSET_AND_MAKE) DESIGN_NAME=${block} DESIGN_NICKNAME=$$(DESIGN_NICKNAME)_${block} DESIGN_CONFIG=./designs/$$(PLATFORM)/$$(DESIGN_NICKNAME)/block.mk generate_abstract
+ $$(UNSET_AND_MAKE) DESIGN_NAME=${block} DESIGN_NICKNAME=$$(DESIGN_NICKNAME)_${block} DESIGN_CONFIG=$$(shell dirname $$(DESIGN_CONFIG))/block.mk generate_abstract
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else
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# There is a unique config.mk for this Verilog module
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