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Merge branch 'master' into secure-mv-repair_tie-to-floorplan
Signed-off-by: Matt Liberty <[email protected]>
2 parents a4fe8af + 9d305d7 commit 8276116

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‎.github/workflows/github-actions-lint-tcl.yml‎

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name: Lint Tcl code
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on:
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push:
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branches:
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- master
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pull_request:
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branches:
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- master
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jobs:
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build:
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runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }}
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steps:
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- name: Checkout repository
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uses: actions/checkout@v4
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- name: Install Dependencies
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run: |
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python3 -m venv venv
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venv/bin/pip install tclint==0.4.2
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- name: Lint
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run: |
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source venv/bin/activate
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tclfmt --version
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tclfmt --in-place .
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git diff --exit-code
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tclint --no-check-style .

‎.github/workflows/github-actions-manual-update-rules.yml‎

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python-version: "3.10"
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- name: Install Python Packages
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run: |
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pip install firebase-admin
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python3 -m venv venv
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venv/bin/pip install firebase-admin
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- name: Execute Python Script Update
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env:
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CREDS_FILE: ${{ secrets.CREDS_FILE }}
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API_BASE_URL: ${{ secrets.API_BASE_URL }}
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run: |
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source venv/bin/activate
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if [[ "${{ github.event.inputs.type }}" == "overwrite" ]]; then
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python flow/util/updateRules.py --keyFile "${CREDS_FILE}" --apiURL ${API_BASE_URL} --commitSHA $(git rev-parse HEAD) --overwrite
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else

‎.github/workflows/github-actions-update-rules.yml‎

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python-version: "3.10"
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- name: Install Python Packages
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run: |
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pip install firebase-admin
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python3 -m venv venv
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venv/bin/pip install firebase-admin
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- name: Execute Python Script Update
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env:
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CREDS_FILE: ${{ secrets.CREDS_FILE }}
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API_BASE_URL: ${{ secrets.API_BASE_URL }}
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run: |
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source ./venv/bin/activate
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echo ${{ github.event_name }}
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echo ${{ github.event.client_payload.type }}
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if [[ "${{ github.event_name }}" == "repository_dispatch" && "${{ github.event.client_payload.type }}" == "overwrite" ]]; then

‎.github/workflows/github-actions-yaml-test.yml‎

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- name: Check if FlowVariables.md is up to date
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run: |
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git diff --exit-code docs/user/FlowVariables.md
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- name: Install dependencies
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run: |
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python3 -m venv venv
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venv/bin/pip install --quiet yamlfix==1.17.0
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- name: Run yamlfix check
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run: |
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pip install --quiet yamlfix==1.17.0
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source venv/bin/activate
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yamlfix --version
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set -x
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yamlfix -c yamlfix.toml flow/scripts/variables.yaml

‎.gitignore‎

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flow/*.tif.gz
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flow/*.def.v
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# RePlAce deps
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*PORT9.dat
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*POST9.dat
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bazel-out
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bazel-OpenROAD-flow-scripts
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bazel-testlogs
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# python venv
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venv/

‎docs/user/FlowVariables.md‎

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| <a name="DONT_USE_CELLS"></a>DONT_USE_CELLS| Dont use cells eases pin access in detailed routing.| |
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| <a name="DONT_USE_LIBS"></a>DONT_USE_LIBS| Set liberty files as `dont_use`.| |
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| <a name="DPO_MAX_DISPLACEMENT"></a>DPO_MAX_DISPLACEMENT| Specifies how far an instance can be moved when optimizing.| 5 1|
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| <a name="EARLY_SIZING_CAP_RATIO"></a>EARLY_SIZING_CAP_RATIO| Ratio between the input pin capacitance and the output pin load during initial gate sizing.| |
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| <a name="ENABLE_DPO"></a>ENABLE_DPO| Enable detail placement with improve_placement feature.| 1|
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| <a name="EQUIVALENCE_CHECK"></a>EQUIVALENCE_CHECK| Enable running equivalence checks to verify logical correctness of repair_timing.| 0|
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| <a name="FASTROUTE_TCL"></a>FASTROUTE_TCL| Specifies a Tcl script with commands to run before FastRoute.| |
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| <a name="TECH_LEF"></a>TECH_LEF| A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.| |
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| <a name="TIEHI_CELL_AND_PORT"></a>TIEHI_CELL_AND_PORT| Tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist.| |
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| <a name="TIELO_CELL_AND_PORT"></a>TIELO_CELL_AND_PORT| Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.| |
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| <a name="TIE_SEPARATION"></a>TIE_SEPARATION| Distance separating tie high/low instances from the load.| |
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| <a name="TNS_END_PERCENT"></a>TNS_END_PERCENT| Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed.| 100|
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| <a name="USE_FILL"></a>USE_FILL| Whether to perform metal density filling.| 0|
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| <a name="VERILOG_DEFINES"></a>VERILOG_DEFINES| Preprocessor defines passed to the language frontend. Example: `-D HPDCACHE_ASSERT_OFF`| |
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- [CELL_PAD_IN_SITES_DETAIL_PLACEMENT](#CELL_PAD_IN_SITES_DETAIL_PLACEMENT)
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- [CELL_PAD_IN_SITES_GLOBAL_PLACEMENT](#CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)
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- [EARLY_SIZING_CAP_RATIO](#EARLY_SIZING_CAP_RATIO)
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- [FLOORPLAN_DEF](#FLOORPLAN_DEF)
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- [GPL_ROUTABILITY_DRIVEN](#GPL_ROUTABILITY_DRIVEN)
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- [GPL_TIMING_DRIVEN](#GPL_TIMING_DRIVEN)
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- [PLACE_PINS_ARGS](#PLACE_PINS_ARGS)
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- [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT)
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- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
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- [TIE_SEPARATION](#TIE_SEPARATION)
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## cts variables
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‎flow/designs/asap7/aes-block/constraint.sdc‎

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set clk_name clk
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set clk_name clk
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set clk_port_name clk
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set clk_period 475
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set clk_io_pct 0.2
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create_clock -name $clk_name -period $clk_period $clk_port
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set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
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set non_clock_inputs [all_inputs -no_clocks]
1111

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set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
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set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
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set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

‎flow/designs/asap7/aes-block/rules-base.json‎

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"compare": "<="
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},
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"cts__design__instance__count__hold_buffer": {
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"value": 1078,
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"value": 1331,
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"compare": "<="
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},
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"globalroute__antenna_diodes_count": {

‎flow/designs/asap7/aes-mbff/constraint.sdc‎

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set clk_name clk
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set clk_name clk
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set clk_port_name clk
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set clk_period 400
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set clk_period 400
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set clk_io_pct 0.2
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set clk_port [get_ports $clk_port_name]
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create_clock -name $clk_name -period $clk_period $clk_port
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set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
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set non_clock_inputs [all_inputs -no_clocks]
1111

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set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
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set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
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set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

‎flow/designs/asap7/aes/constraint.sdc‎

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set clk_name clk
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set clk_name clk
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set clk_port_name clk
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set clk_period 400
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set clk_period 400
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set clk_io_pct 0.2
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set clk_port [get_ports $clk_port_name]
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create_clock -name $clk_name -period $clk_period $clk_port
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set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
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set non_clock_inputs [all_inputs -no_clocks]
1111

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set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
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set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
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set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

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