mock-array-big/Element: Directional port names

Co-authored-by: Øyvind Harboe <[email protected]>

Signed-off-by: Jake Taylor <[email protected]>
Signed-off-by: Øyvind Harboe <[email protected]>

Author: yupferris

flow/designs/asap7/mock-array-big/Element/io.tcl

@@ -11,21 +11,21 @@ set data_width [expr {[info exists ::env(MOCK_ARRAY_DATAWIDTH)] ? $::env(MOCK_AR
 set assignments [list \
     top bottom \
     [list [ concat \
-        {*}[pin1 {io_ins_2[%d]} $data_width] \
-        {*}[pin1 {io_outs_2[%d]} $data_width] \
+        {*}[pin1 {io_ins_down[%d]} $data_width] \
+        {*}[pin1 {io_outs_up[%d]} $data_width] \
     ] \
     [ concat \
-        {*}[pin1 {io_outs_0[%d]} $data_width] \
-        {*}[pin1 {io_ins_0[%d]} $data_width] \
+        {*}[pin1 {io_outs_down[%d]} $data_width] \
+        {*}[pin1 {io_ins_up[%d]} $data_width] \
     ]] \
     left right \
     [list [ concat \
-        {*}[pin1 {io_ins_3[%d]} $data_width] \
-        {*}[pin1 {io_outs_3[%d]} $data_width] \
+        {*}[pin1 {io_ins_right[%d]} $data_width] \
+        {*}[pin1 {io_outs_left[%d]} $data_width] \
     ] \
     [ concat \
-        {*}[pin1 {io_outs_1[%d]} $data_width] \
-        {*}[pin1 {io_ins_1[%d]} $data_width] \
+        {*}[pin1 {io_outs_right[%d]} $data_width] \
+        {*}[pin1 {io_ins_left[%d]} $data_width] \
     ]] \
 ]
 

flow/designs/src/mock-array-big/Element.v

@@ -1,33 +1,33 @@
 module Element(
   input        clock,
-  input  [7:0] io_ins_0,
-  input  [7:0] io_ins_1,
-  input  [7:0] io_ins_2,
-  input  [7:0] io_ins_3,
-  output [7:0] io_outs_0,
-  output [7:0] io_outs_1,
-  output [7:0] io_outs_2,
-  output [7:0] io_outs_3
+  input  [7:0] io_ins_down, // @[src/test/scala/MockArray.scala 50:9]
+  input  [7:0] io_ins_right, // @[src/test/scala/MockArray.scala 50:9]
+  input  [7:0] io_ins_up, // @[src/test/scala/MockArray.scala 50:9]
+  input  [7:0] io_ins_left, // @[src/test/scala/MockArray.scala 50:9]
+  output [7:0] io_outs_down, // @[src/test/scala/MockArray.scala 50:9]
+  output [7:0] io_outs_right, // @[src/test/scala/MockArray.scala 50:9]
+  output [7:0] io_outs_up, // @[src/test/scala/MockArray.scala 50:9]
+  output [7:0] io_outs_left // @[src/test/scala/MockArray.scala 50:9]
 );
 `ifdef RANDOMIZE_REG_INIT
   reg [31:0] _RAND_0;
   reg [31:0] _RAND_1;
   reg [31:0] _RAND_2;
   reg [31:0] _RAND_3;
 `endif // RANDOMIZE_REG_INIT
-  reg [7:0] REG; // @[MockArray.scala 33:42]
-  reg [7:0] REG_1; // @[MockArray.scala 33:42]
-  reg [7:0] REG_2; // @[MockArray.scala 33:42]
-  reg [7:0] REG_3; // @[MockArray.scala 33:42]
-  assign io_outs_0 = REG; // @[MockArray.scala 33:13]
-  assign io_outs_1 = REG_1; // @[MockArray.scala 33:13]
-  assign io_outs_2 = REG_2; // @[MockArray.scala 33:13]
-  assign io_outs_3 = REG_3; // @[MockArray.scala 33:13]
+  reg [7:0] REG; // @[src/test/scala/MockArray.scala 54:56]
+  reg [7:0] REG_1; // @[src/test/scala/MockArray.scala 54:56]
+  reg [7:0] REG_2; // @[src/test/scala/MockArray.scala 54:56]
+  reg [7:0] REG_3; // @[src/test/scala/MockArray.scala 54:56]
+  assign io_outs_down = REG_3; // @[src/test/scala/MockArray.scala 54:87]
+  assign io_outs_right = REG_2; // @[src/test/scala/MockArray.scala 54:87]
+  assign io_outs_up = REG_1; // @[src/test/scala/MockArray.scala 54:87]
+  assign io_outs_left = REG; // @[src/test/scala/MockArray.scala 54:87]
   always @(posedge clock) begin
-    REG <= io_ins_3; // @[MockArray.scala 33:42]
-    REG_1 <= io_ins_2; // @[MockArray.scala 33:42]
-    REG_2 <= io_ins_1; // @[MockArray.scala 33:42]
-    REG_3 <= io_ins_0; // @[MockArray.scala 33:42]
+    REG <= io_ins_down; // @[src/test/scala/MockArray.scala 54:56]
+    REG_1 <= io_ins_right; // @[src/test/scala/MockArray.scala 54:56]
+    REG_2 <= io_ins_up; // @[src/test/scala/MockArray.scala 54:56]
+    REG_3 <= io_ins_left; // @[src/test/scala/MockArray.scala 54:56]
   end
 // Register and memory initialization
 `ifdef RANDOMIZE_GARBAGE_ASSIGN