Merge pull request #3702 from The-OpenROAD-Project-staging/synth-dff-mapping

added DFF_MAP_FILE flow variable to map DFF's

Author: maliberty

docs/user/FlowVariables.md

@@ -95,7 +95,7 @@ configuration file.
 | <a name="ABC_DRIVER_CELL"></a>ABC_DRIVER_CELL| Default driver cell used during ABC synthesis.| |
 | <a name="ABC_LOAD_IN_FF"></a>ABC_LOAD_IN_FF| During synthesis set_load value used.| |
 | <a name="ABSTRACT_SOURCE"></a>ABSTRACT_SOURCE| Which .odb file to use to create abstract| |
-| <a name="ADDER_MAP_FILE"></a>ADDER_MAP_FILE| List of adders treated as a black box by Yosys.| |
+| <a name="ADDER_MAP_FILE"></a>ADDER_MAP_FILE| Optional mapping file supplied to Yosys to map adders| |
 | <a name="ADDITIONAL_FILES"></a>ADDITIONAL_FILES| Additional files to be added to `make issue` archive.| |
 | <a name="ADDITIONAL_GDS"></a>ADDITIONAL_GDS| Hardened macro GDS files listed here.| |
 | <a name="ADDITIONAL_LEFS"></a>ADDITIONAL_LEFS| Hardened macro LEF view files listed here. The LEF information of the macros is immutable and used throughout all stages. Stored in the .odb file.| |
@@ -107,7 +107,7 @@ configuration file.
 | <a name="CDL_FILES"></a>CDL_FILES| Insert additional Circuit Description Language (`.cdl`) netlist files.| |
 | <a name="CELL_PAD_IN_SITES_DETAIL_PLACEMENT"></a>CELL_PAD_IN_SITES_DETAIL_PLACEMENT| Cell padding on both sides in site widths to ease routability in detail placement.| 0|
 | <a name="CELL_PAD_IN_SITES_GLOBAL_PLACEMENT"></a>CELL_PAD_IN_SITES_GLOBAL_PLACEMENT| Cell padding on both sides in site widths to ease routability during global placement.| 0|
-| <a name="CLKGATE_MAP_FILE"></a>CLKGATE_MAP_FILE| List of cells for gating clock treated as a black box by Yosys.| |
+| <a name="CLKGATE_MAP_FILE"></a>CLKGATE_MAP_FILE| Optional mapping file supplied to Yosys to map clock gating cells| |
 | <a name="CLUSTER_FLOPS"></a>CLUSTER_FLOPS| Minimum number of flip-flops per sink cluster.| 0|
 | <a name="CORE_AREA"></a>CORE_AREA| The core area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| |
 | <a name="CORE_ASPECT_RATIO"></a>CORE_ASPECT_RATIO| The core aspect ratio (height / width). This value is ignored if `CORE_UTILIZATION` is undefined.| 1.0|
@@ -128,6 +128,7 @@ configuration file.
 | <a name="DETAILED_ROUTE_ARGS"></a>DETAILED_ROUTE_ARGS| Add additional arguments for debugging purposes during detail route.| |
 | <a name="DETAILED_ROUTE_END_ITERATION"></a>DETAILED_ROUTE_END_ITERATION| Maximum number of iterations.| 64|
 | <a name="DFF_LIB_FILES"></a>DFF_LIB_FILES| Technology mapping liberty files for flip-flops.| |
+| <a name="DFF_MAP_FILE"></a>DFF_MAP_FILE| Optional mapping file supplied to Yosys to map D flip-flops| |
 | <a name="DIE_AREA"></a>DIE_AREA| The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| |
 | <a name="DONT_BUFFER_PORTS"></a>DONT_BUFFER_PORTS| Do not buffer input/output ports during floorplanning.| 0|
 | <a name="DONT_USE_CELLS"></a>DONT_USE_CELLS| Dont use cells eases pin access in detailed routing.| |
@@ -157,7 +158,7 @@ configuration file.
 | <a name="IO_PLACER_V"></a>IO_PLACER_V| A list of metal layers on which the I/O pins are placed vertically (sides of the die).| |
 | <a name="IR_DROP_LAYER"></a>IR_DROP_LAYER| Default metal layer to report IR drop.| |
 | <a name="KLAYOUT_TECH_FILE"></a>KLAYOUT_TECH_FILE| A mapping from LEF/DEF to GDS using the KLayout tool.| |
-| <a name="LATCH_MAP_FILE"></a>LATCH_MAP_FILE| List of latches treated as a black box by Yosys.| |
+| <a name="LATCH_MAP_FILE"></a>LATCH_MAP_FILE| Optional mapping file supplied to Yosys to map latches| |
 | <a name="LIB_FILES"></a>LIB_FILES| A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell.| |
 | <a name="MACRO_BLOCKAGE_HALO"></a>MACRO_BLOCKAGE_HALO| Distance beyond the edges of a macro that will also be covered by the blockage generated for that macro. Note that the default macro blockage halo comes from the largest of the specified MACRO_PLACE_HALO x or y values. This variable overrides that calculation.| |
 | <a name="MACRO_EXTENSION"></a>MACRO_EXTENSION| Sets the number of GCells added to the blockages boundaries from macros.| |
@@ -276,6 +277,7 @@ configuration file.
 - [ABC_LOAD_IN_FF](#ABC_LOAD_IN_FF)
 - [ADDER_MAP_FILE](#ADDER_MAP_FILE)
 - [CLKGATE_MAP_FILE](#CLKGATE_MAP_FILE)
+- [DFF_MAP_FILE](#DFF_MAP_FILE)
 - [LATCH_MAP_FILE](#LATCH_MAP_FILE)
 - [MIN_BUF_CELL_AND_PORTS](#MIN_BUF_CELL_AND_PORTS)
 - [SDC_FILE](#SDC_FILE)

flow/scripts/synth.tcl

@@ -1,3 +1,36 @@
+#
+# Extracts and returns module names from Verilog file
+#
+proc get_module_names { file_path } {
+  set module_list [list]
+  if { [catch { set fid [open $file_path r] } err] } {
+    error "Failed to open file $file_path: $err"
+  }
+
+  set regex {^[ \t]*module[ \t]+([A-Za-z_$][A-Za-z0-9_$]*)}
+
+  while { [gets $fid line] >= 0 } {
+    if { [regexp -nocase $regex $line match_all module_name] } {
+      lappend module_list $module_name
+    }
+  }
+
+  close $fid
+  return $module_list
+}
+
+#
+# Builds dfflegalize arg list
+#
+proc get_dfflegalize_args { file_path } {
+  set legalize_args [list]
+  set module_names [get_module_names $file_path]
+  foreach module_name $module_names {
+    lappend legalize_args -cell $module_name x
+  }
+  return $legalize_args
+}
+
 source $::env(SCRIPTS_DIR)/synth_preamble.tcl
 read_checkpoint $::env(RESULTS_DIR)/1_1_yosys_canonicalize.rtlil
 
@@ -143,6 +176,10 @@ if { [env_var_exists_and_non_empty LATCH_MAP_FILE] } {
 # dfflibmap only supports one liberty file
 if { [env_var_exists_and_non_empty DFF_LIB_FILE] } {
   dfflibmap -liberty $::env(DFF_LIB_FILE) {*}$lib_dont_use_args
+} elseif { [env_var_exists_and_non_empty DFF_MAP_FILE] } {
+  set legalize_args [get_dfflegalize_args $::env(DFF_MAP_FILE)]
+  dfflegalize {*}$legalize_args
+  techmap -map $::env(DFF_MAP_FILE)
 } else {
   dfflibmap {*}$lib_args {*}$lib_dont_use_args
 }

flow/scripts/variables.yaml

@@ -292,19 +292,24 @@ SYNTH_RETIME_MODULES:
     optimal distribution of registers on long pipelines. See OR discussion #8080.
   stages:
     - synth
+DFF_MAP_FILE:
+  description: |
+    Optional mapping file supplied to Yosys to map D flip-flops
+  stages:
+    - synth
 LATCH_MAP_FILE:
   description: |
-    List of latches treated as a black box by Yosys.
+    Optional mapping file supplied to Yosys to map latches
   stages:
     - synth
 CLKGATE_MAP_FILE:
   description: |
-    List of cells for gating clock treated as a black box by Yosys.
+    Optional mapping file supplied to Yosys to map clock gating cells
   stages:
     - synth
 ADDER_MAP_FILE:
   description: |
-    List of adders treated as a black box by Yosys.
+    Optional mapping file supplied to Yosys to map adders
   stages:
     - synth
 TIEHI_CELL_AND_PORT: