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Merge branch 'master' into pdn-pins-layer
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‎docs/user/FlowVariables.md‎

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@@ -214,6 +214,7 @@ configuration file.
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| <a name="SETUP_SLACK_MARGIN"></a>SETUP_SLACK_MARGIN| Specifies a time margin for the slack when fixing setup violations. This option allows you to overfix or underfix(negative value, terminate retiming before 0 or positive slack). See HOLD_SLACK_MARGIN for more details.| 0|
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| <a name="SET_RC_TCL"></a>SET_RC_TCL| Metal & Via RC definition file path.| |
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| <a name="SKIP_CTS_REPAIR_TIMING"></a>SKIP_CTS_REPAIR_TIMING| Skipping CTS repair, which can take a long time, can be useful in architectural exploration or when getting CI up and running.| |
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| <a name="SKIP_DETAILED_ROUTE"></a>SKIP_DETAILED_ROUTE| Skips detailed route.| 0|
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| <a name="SKIP_GATE_CLONING"></a>SKIP_GATE_CLONING| Do not use gate cloning transform to fix timing violations (default: use gate cloning).| |
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| <a name="SKIP_INCREMENTAL_REPAIR"></a>SKIP_INCREMENTAL_REPAIR| Skip incremental repair in global route.| 0|
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| <a name="SKIP_LAST_GASP"></a>SKIP_LAST_GASP| Do not use last gasp optimization to fix timing violations (default: use gate last gasp).| |
@@ -411,6 +412,7 @@ configuration file.
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- [MIN_ROUTING_LAYER](#MIN_ROUTING_LAYER)
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- [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW)
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- [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT)
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- [SKIP_DETAILED_ROUTE](#SKIP_DETAILED_ROUTE)
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- [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
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## final variables

‎flow/designs/asap7/cva6/canonicalize.tcl‎

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# Remove rvfi_probes_o interface since contributes 4k ports and connections
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# (many of which are buffers tied to tie cells)
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delete cva6/o:rvfi_probes_o*

‎flow/designs/asap7/cva6/config.mk‎

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@@ -105,3 +105,6 @@ export SYNTH_HDL_FRONTEND = slang
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export ASAP7_USE_VT = RVT LVT SLVT
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export CTS_LIB_NAME = asap7sc7p5t_INVBUF_SLVT_FF_nldm_211120
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# Remove rvfi_probes_o interface
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export SYNTH_CANONICALIZE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/canonicalize.tcl

‎flow/designs/asap7/cva6/rules-base.json‎

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{
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"synth__design__instance__area__stdcell": {
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"value": 19725.15,
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"value": 18975.35,
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"compare": "<="
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},
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"constraints__clocks__count": {
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"value": 1,
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"compare": "=="
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},
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"placeopt__design__instance__area": {
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"value": 20690,
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"value": 19709,
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"compare": "<="
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},
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"placeopt__design__instance__count__stdcell": {
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"value": 136421,
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"value": 123443,
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"compare": "<="
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},
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"detailedplace__design__violations": {
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"value": 0,
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"compare": "=="
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},
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"cts__design__instance__count__setup_buffer": {
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"value": 11863,
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"value": 10734,
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"compare": "<="
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},
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"cts__design__instance__count__hold_buffer": {
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"value": 11863,
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"value": 10734,
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"compare": "<="
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},
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"globalroute__antenna_diodes_count": {
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"value": 0,
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"compare": "<="
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},
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"detailedroute__route__wirelength": {
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"value": 1074578,
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"value": 716033,
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"compare": "<="
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},
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"detailedroute__route__drc_errors": {
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"compare": "<="
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},
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"finish__timing__setup__ws": {
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"value": -139.89,
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"value": -82.95,
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"compare": ">="
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},
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"finish__design__instance__area": {
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"value": 20850,
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"value": 19864,
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"compare": "<="
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},
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"finish__timing__drv__setup_violation_count": {
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"value": 5931,
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"value": 5367,
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"compare": "<="
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},
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"finish__timing__drv__hold_violation_count": {

‎flow/designs/ihp-sg13g2/spi/rules-base.json‎

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"compare": "<="
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},
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"detailedroute__route__wirelength": {
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"value": 4888,
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"value": 4553,
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"compare": "<="
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},
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"detailedroute__route__drc_errors": {
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"compare": "<="
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},
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"finish__timing__setup__ws": {
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"value": -0.09,
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"value": -0.07,
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"compare": ">="
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},
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"finish__design__instance__area": {
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"value": 10383,
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"value": 10376,
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"compare": "<="
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},
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"finish__timing__drv__setup_violation_count": {
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"value": 10,
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"value": 14,
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"compare": "<="
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},
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"finish__timing__drv__hold_violation_count": {
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"value": 10,
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"compare": "<="
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},
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"finish__timing__wns_percent_delay": {
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"value": -15.68,
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"value": -13.57,
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"compare": ">="
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}
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}

‎flow/designs/rapidus2hp/cva6/config.mk‎

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@@ -102,7 +102,12 @@ ifeq ($(SYNTH_HDL_FRONTEND),verific)
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else
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# Reduce the amount of resizing done between GPL and DPL
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export EARLY_SIZING_CAP_RATIO = 6
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export CORE_UTILIZATION = 55
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ifeq ($(PLACE_SITE),SC6T)
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# Decrease the utilization so that the tall macros fit
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export CORE_UTILIZATION = 50
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else
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export CORE_UTILIZATION = 55
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endif
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endif
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export CORE_MARGIN = 2

‎flow/designs/rapidus2hp/ethmac/constraint.sdc‎

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@@ -22,7 +22,7 @@ set_output_delay [expr { $tx_clk_period * $clk_io_pct }] -clock $tx_clk_name \
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set rx_clk_name mrx_clk_pad_i
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set rx_clk_port [get_ports $rx_clk_name]
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set rx_clk_period 300
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set rx_clk_period 200
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create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
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set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] \
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$rx_clk_port]

‎flow/designs/rapidus2hp/gcd/constraint.sdc‎

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set clk_name core_clock
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set clk_port_name clk
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set clk_period 185
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set clk_period 150
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set clk_io_pct 0.2
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set clk_port [get_ports $clk_port_name]

‎flow/designs/rapidus2hp/hercules_is_int/config.mk‎

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export SYNTH_HDL_FRONTEND = slang
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export SYNTH_HIERARCHICAL ?= 0
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export CORE_UTILIZATION = 35
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ifeq ($(PLACE_SITE), SC6T)
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export CORE_UTILIZATION = 30
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else
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export CORE_UTILIZATION = 35
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endif
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export CORE_MARGIN = 2
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export MACRO_PLACE_HALO = 2 2

‎flow/scripts/detail_route.tcl‎

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@@ -5,15 +5,19 @@ if { ![grt::have_routes] } {
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error "Global routing failed, run `make gui_grt` and load $::global_route_congestion_report \
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in DRC viewer to view congestion"
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}
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if { [env_var_exists_and_non_empty SKIP_DRT] } {
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write_db $::env(RESULTS_DIR)/5_2_route.odb
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exit
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}
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erase_non_stage_variables route
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set_propagated_clock [all_clocks]
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set additional_args ""
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append_env_var additional_args dbProcessNode -db_process_node 1
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append_env_var additional_args OR_SEED -or_seed 1
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append_env_var additional_args OR_K -or_k 1
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append_env_var additional_args MIN_ROUTING_LAYER -bottom_routing_layer 1
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append_env_var additional_args MAX_ROUTING_LAYER -top_routing_layer 1
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append_env_var additional_args VIA_IN_PIN_MIN_LAYER -via_in_pin_bottom_layer 1
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append_env_var additional_args VIA_IN_PIN_MAX_LAYER -via_in_pin_top_layer 1
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append_env_var additional_args DISABLE_VIA_GEN -disable_via_gen 0

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