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docs: extend VERILOG_TOP_PARAMS a bit
Signed-off-by: Øyvind Harboe <[email protected]>
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docs/user/FlowVariables.md

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@@ -270,7 +270,7 @@ configuration file.
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| <a name="VERILOG_DEFINES"></a>VERILOG_DEFINES| Preprocessor defines passed to the language frontend. Example: `-D HPDCACHE_ASSERT_OFF`| |
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| <a name="VERILOG_FILES"></a>VERILOG_FILES| The path to the design Verilog/SystemVerilog files providing a description of modules.| |
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| <a name="VERILOG_INCLUDE_DIRS"></a>VERILOG_INCLUDE_DIRS| Specifies the include directories for the Verilog input files.| |
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| <a name="VERILOG_TOP_PARAMS"></a>VERILOG_TOP_PARAMS| Apply toplevel params (if exist).| |
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| <a name="VERILOG_TOP_PARAMS"></a>VERILOG_TOP_PARAMS| Apply toplevel params (if exist). Passed in as a list of key value pairs in tcl syntax; separated by spaces: PARAM1 VALUE1 PARAM2 VALUE2 stages: - synth| |
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| <a name="YOSYS_FLAGS"></a>YOSYS_FLAGS| Flags to pass to yosys.| -v 3|
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## synth variables
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- [VERILOG_DEFINES](#VERILOG_DEFINES)
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- [VERILOG_FILES](#VERILOG_FILES)
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- [VERILOG_INCLUDE_DIRS](#VERILOG_INCLUDE_DIRS)
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- [VERILOG_TOP_PARAMS](#VERILOG_TOP_PARAMS)
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- [YOSYS_FLAGS](#YOSYS_FLAGS)
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## floorplan variables
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- [TAP_CELL_NAME](#TAP_CELL_NAME)
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- [TECH_LEF](#TECH_LEF)
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- [USE_FILL](#USE_FILL)
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- [VERILOG_TOP_PARAMS](#VERILOG_TOP_PARAMS)
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flow/scripts/variables.yaml

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@@ -873,8 +873,9 @@ SYNTH_OPT_HIER:
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- synth
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VERILOG_TOP_PARAMS:
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description: |
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Apply toplevel params (if exist).
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stages:
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Apply toplevel params (if exist). Passed in as a list of key value pairs
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in tcl syntax; separated by spaces: PARAM1 VALUE1 PARAM2 VALUE2
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stages:
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- synth
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CORE_ASPECT_RATIO:
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description: >

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