asap7: move behavioral logic files into platform dir

Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

flow/designs/asap7/mock-array/power.tcl

@@ -6,7 +6,7 @@ foreach libFile $::env(LIB_FILES) {
 
 read_verilog results/asap7/mock-array_Element/base/6_final.v
 read_verilog $::env(RESULTS_DIR)/6_final.v
-read_verilog designs/src/mock-array/post/empty.v
+read_verilog $::env(PLATFORM_DIR)/verilog/stdcell/empty.v
 
 link_design MockArray
 

flow/designs/src/mock-array/.gitignore

@@ -7,3 +7,4 @@ target/
 .bloop/
 .bsp/
 test_run_dir/
+MockArrayTestbench.vcd

flow/designs/src/mock-array/src/main/scala/MockArray.scala

@@ -161,16 +161,17 @@ extends BlackBox with HasBlackBoxPath {
     val reset = Input(Bool())
     val io = new MockArrayBundle(width, height, singleElementWidth)
   })
-  Seq("asap7sc7p5t_AO_RVT_TT_201020.v",
+  val platformDir = sys.env.getOrElse("PLATFORM_DIR", "defaultPath") + "/verilog/stdcell/"
+  (Seq("asap7sc7p5t_AO_RVT_TT_201020.v",
     "asap7sc7p5t_SEQ_RVT_TT_220101.v",
     "asap7sc7p5t_SIMPLE_RVT_TT_201020.v",
     "asap7sc7p5t_INVBUF_RVT_TT_201020.v",
     "empty.v",
-    "dff.v",
+    "dff.v").map(p=>Paths.get(platformDir + p)) ++
+    Seq(
   "MockArrayFinal.v",
-  "MockArrayElementFinal.v").foreach{
-    path => addPath(Paths.get("post/" + path).toAbsolutePath().toString())
-  }
+  "MockArrayElementFinal.v").map(p=>Paths.get("post/" + p)))
+  .foreach(p=> addPath(p.toAbsolutePath().toString()))
 }
 
 class MockArrayTestbench(width:Int, height:Int, singleElementWidth:Int) extends Module {

flow/platforms/asap7/verilog/stdcell/README.md

@@ -0,0 +1,15 @@
+ASAP7 behavioral model files
+============================
+
+These are unmodified files from
+https://github.com/The-OpenROAD-Project/asap7sc7p5t_28/tree/main/Verilog
+
+Note that some tools, notably Verilator, might struggle with some
+of the SystemVerilog features used by the behavioral logic files in
+the ASAP7 PDK.
+
+To work around this ORFS re-implements some behavioral such as the dff.v
+and empty.v to allow for post-synthesis simulation to use OpenSTA
+read_power_activities features.
+
+

…rray/post/asap7sc7p5t_AO_RVT_TT_201020.v …g/stdcell/asap7sc7p5t_AO_RVT_TT_201020.vflow/designs/src/mock-array/post/asap7sc7p5t_AO_RVT_TT_201020.v renamed to flow/platforms/asap7/verilog/stdcell/asap7sc7p5t_AO_RVT_TT_201020.v flow/designs/src/mock-array/post/asap7sc7p5t_AO_RVT_TT_201020.v renamed to flow/platforms/asap7/verilog/stdcell/asap7sc7p5t_AO_RVT_TT_201020.v

@@ -1,3 +1,8 @@
+// Quick and dirty reimplementation of altos_dff_module because
+// Verilato doesn't support and has no plans to support 1995 UDP
+// tables.
+//
+// https://github.com/verilator/verilator/issues/5243
 module altos_dff_module(q, v, clk, d, xcr);
     output reg q;
     input v, clk, d, xcr;

…/post/asap7sc7p5t_INVBUF_RVT_TT_201020.v …dcell/asap7sc7p5t_INVBUF_RVT_TT_201020.vflow/designs/src/mock-array/post/asap7sc7p5t_INVBUF_RVT_TT_201020.v renamed to flow/platforms/asap7/verilog/stdcell/asap7sc7p5t_INVBUF_RVT_TT_201020.v flow/designs/src/mock-array/post/asap7sc7p5t_INVBUF_RVT_TT_201020.v renamed to flow/platforms/asap7/verilog/stdcell/asap7sc7p5t_INVBUF_RVT_TT_201020.v

@@ -1,3 +1,4 @@
+// Used to silence warnings.
 module TAPCELL_ASAP7_75t_R;
 endmodule
 module FILLERxp5_ASAP7_75t_R;