added max_fanout=10 to asap7/cva6 and added SKIP_CRIT_VT_SWAP option

Signed-off-by: Cho Moon <[email protected]>

Author: precisionmoon

docs/user/FlowVariables.md

@@ -225,6 +225,7 @@ configuration file.
 | <a name="SKIP_REPAIR_TIE_FANOUT"></a>SKIP_REPAIR_TIE_FANOUT| Skip repair_tie_fanout at floorplan step.| |
 | <a name="SKIP_REPORT_METRICS"></a>SKIP_REPORT_METRICS| If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.| |
 | <a name="SKIP_VT_SWAP"></a>SKIP_VT_SWAP| Do not perform VT swap to improve QoR (default: do VT swap).| |
+| <a name="SKIP_CRIT_VT_SWAP"></a>SKIP_CRIT_VT_SWAP| Do not perform VT swap on critical cells to improve QoR (default: do critical VT swap).| |
 | <a name="SLEW_MARGIN"></a>SLEW_MARGIN| Specifies a slew margin when fixing max slew violations. This option allows you to overfix.| |
 | <a name="SWAP_ARITH_OPERATORS"></a>SWAP_ARITH_OPERATORS| Improve timing QoR by swapping ALU and MULT arithmetic operators.| |
 | <a name="SYNTH_ARGS"></a>SYNTH_ARGS| Optional synthesis variables for yosys.| |
@@ -341,6 +342,7 @@ configuration file.
 - [SKIP_REPAIR_TIE_FANOUT](#SKIP_REPAIR_TIE_FANOUT)
 - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
 - [SKIP_VT_SWAP](#SKIP_VT_SWAP)
+- [SKIP_CRIT_VT_SWAP](#SKIP_CRIT_VT_SWAP)
 - [TAPCELL_TCL](#TAPCELL_TCL)
 - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
 - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)
@@ -391,6 +393,7 @@ configuration file.
 - [SKIP_PIN_SWAP](#SKIP_PIN_SWAP)
 - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
 - [SKIP_VT_SWAP](#SKIP_VT_SWAP)
+- [SKIP_CRIT_VT_SWAP](#SKIP_CRIT_VT_SWAP)
 - [TNS_END_PERCENT](#TNS_END_PERCENT)
 
 ## grt variables
@@ -413,6 +416,7 @@ configuration file.
 - [SKIP_PIN_SWAP](#SKIP_PIN_SWAP)
 - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
 - [SKIP_VT_SWAP](#SKIP_VT_SWAP)
+- [SKIP_CRIT_VT_SWAP](#SKIP_CRIT_VT_SWAP)
 - [TNS_END_PERCENT](#TNS_END_PERCENT)
 
 ## route variables

flow/designs/asap7/cva6/config.mk

@@ -95,7 +95,7 @@ export PLACE_DENSITY          = 0.69
 
 # a smoketest for this option, there are a
 # few last gasp iterations
-export SKIP_LAST_GASP ?= 1
+#export SKIP_LAST_GASP ?= 1
 
 # For use with SYNTH_HIERARCHICAL
 export SYNTH_MINIMUM_KEEP_SIZE ?= 40000

flow/designs/asap7/cva6/constraint.sdc

@@ -34,3 +34,4 @@ create_clock [get_ports $clk_port] -name $clk_name -period $clk_period
 
 
 set_false_path -to [get_ports {rvfi_probes_o}]
+set_max_fanout 10 [current_design]

flow/scripts/util.tcl

@@ -26,6 +26,7 @@ proc repair_timing_helper { args } {
   append_env_var additional_args SKIP_BUFFER_REMOVAL -skip_buffer_removal 0
   append_env_var additional_args SKIP_LAST_GASP -skip_last_gasp 0
   append_env_var additional_args SKIP_VT_SWAP -skip_vt_swap 0
+  append_env_var additional_args SKIP_CRIT_VT_SWAP -skip_crit_vt_swap 0
   append_env_var additional_args MATCH_CELL_FOOTPRINT -match_cell_footprint 0
   log_cmd repair_timing {*}$additional_args
 }

flow/scripts/variables.yaml

@@ -577,6 +577,15 @@ SKIP_VT_SWAP:
     - cts
     - floorplan
     - grt
+SKIP_CRIT_VT_SWAP:
+  description: >
+    Do not perform VT swap on critical cells to improve QoR (default: do critical VT swap).
+    This is an additional VT swap on critical cells that remain near the end of setup fixing.
+    If SKIP_VT_SWAP is set to 1, this also disables critical cell VT swap.
+  stages:
+    - cts
+    - floorplan
+    - grt
 REMOVE_CELLS_FOR_EQY:
   description: >
     String patterns directly passed to write_verilog -remove_cells <> for