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malibertymaliberty
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Merge pull request #1232 from The-OpenROAD-Project-staging/mb@update
Megaboom Update - To Facilitate Routing
2 parents 045a4f4 + 1b2bb4e commit 8c890b6

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6 files changed

+494
-181
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6 files changed

+494
-181
lines changed

‎flow/designs/asap7/megaboom/config.mk‎

Lines changed: 28 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -9,24 +9,46 @@ export VERILOG_FILES += $(realpath ./designs/src/$(DESIGN_NICKNAME)/rock
99
export SDC_FILE = $(realpath ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc)
1010
export SYNTH_SDC_FILE = $(SDC_FILE)
1111

12-
export CORE_UTILIZATION = 40
13-
export CORE_ASPECT_RATIO = 1
14-
export CORE_MARGIN = 5
1512
export PLACE_DENSITY_LB_ADDON = 0.05
1613

14+
export PDN_TCL = $(dir $(DESIGN_CONFIG))/pdn.tcl
15+
16+
# pre set CORE and DIE to avoid MPL
17+
# add IO and MACRO pre placement
18+
export CORE_AREA = 2.538 2.700 1397.466 1397.250
19+
export DIE_AREA = 0 0 1400 1400
20+
21+
export IO_CONSTRAINTS = $(dir $(DESIGN_CONFIG))/io.tcl
22+
export MACRO_PLACEMENT_TCL = $(dir $(DESIGN_CONFIG))/macro-placement.tcl
23+
24+
# LIB and LEF files for memories and register files used
1725
export BC_ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/fakeram_256x128.lib \
1826
$(PLATFORM_DIR)/lib/fakeram_256x64.lib \
1927
$(PLATFORM_DIR)/lib/fakeram_32x46.lib \
2028
$(PLATFORM_DIR)/lib/fakeram_512x8.lib \
2129
$(PLATFORM_DIR)/lib/fakeram_64x20.lib \
22-
$(PLATFORM_DIR)/lib/fakeram_64x22.lib
30+
$(PLATFORM_DIR)/lib/fakeram_64x22.lib \
31+
$(PLATFORM_DIR)/lib/fakeregfile_32x46.lib \
32+
$(PLATFORM_DIR)/lib/fakeregfile_64x64.lib \
33+
$(PLATFORM_DIR)/lib/fakeregfile_128x64.lib
2334

2435
export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/fakeram_256x128.lef \
2536
$(PLATFORM_DIR)/lef/fakeram_256x64.lef \
2637
$(PLATFORM_DIR)/lef/fakeram_32x46.lef \
2738
$(PLATFORM_DIR)/lef/fakeram_512x8.lef \
2839
$(PLATFORM_DIR)/lef/fakeram_64x20.lef \
29-
$(PLATFORM_DIR)/lef/fakeram_64x22.lef
40+
$(PLATFORM_DIR)/lef/fakeram_64x22.lef \
41+
$(PLATFORM_DIR)/lef/fakeregfile_32x46.lef \
42+
$(PLATFORM_DIR)/lef/fakeregfile_64x64.lef \
43+
$(PLATFORM_DIR)/lef/fakeregfile_128x64.lef
44+
45+
46+
export SYNTH_ARGS ?= -noshare
3047

48+
# since this will be either top level macro or chip itself, allow routing to top of the
49+
# metal stack
50+
export MIN_ROUTING_LAYER = M2
51+
export MAX_ROUTING_LAYER = M9
3152

32-
#export CACHED_NETLIST = $(realpath ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/MegaBoom.v)
53+
export GND_NETS_VOLTAGES = ""
54+
export PWR_NETS_VOLTAGES = ""

‎flow/designs/asap7/megaboom/constraint.sdc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
set clk_name clock
22
set clk_port_name clock
3-
set clk_period 5000
3+
set clk_period 7500
44
set clk_io_pct 0.2
55

66
set clk_port [get_ports $clk_port_name]

‎flow/designs/asap7/megaboom/io.tcl‎

Lines changed: 133 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,133 @@
1+
proc natural_sort {list} {
2+
return [lsort -command natural_compare $list]
3+
}
4+
5+
# Custom comparison function
6+
proc natural_compare {str1 str2} {
7+
set list1 [split $str1]
8+
set list2 [split $str2]
9+
set len [expr {min([llength $list1], [llength $list2])}]
10+
for {set i 0} {$i < $len} {incr i} {
11+
set part1 [lindex $list1 $i]
12+
set part2 [lindex $list2 $i]
13+
if {$part1 ne $part2} {
14+
if {[string is integer -strict $part1] && [string is integer -strict $part2]} {
15+
return [expr {$part1 - $part2}]
16+
} else {
17+
return [string compare $part1 $part2]
18+
}
19+
}
20+
}
21+
return [expr {[llength $list1] - [llength $list2]}] ;# If all parts are equal, compare by length
22+
}
23+
24+
# return regular expression
25+
proc match_pins { regex } {
26+
set pins {}
27+
# The regex for get_ports is not the tcl regex
28+
foreach pin [get_ports -regex .*] {
29+
set input [get_property $pin name]
30+
# We want the Tcl regex
31+
if {![regexp $regex $input]} {
32+
continue
33+
}
34+
lappend pins [get_property $pin name]
35+
}
36+
return [natural_sort $pins]
37+
}
38+
39+
#--------------------------------------------------------------------------------
40+
set block [ord::get_db_block]
41+
42+
# set metal pitch for used with pin placment
43+
# should be set to minimum of 2 tracks
44+
set m4pitch 0.048
45+
set m5pitch 0.048
46+
47+
# create array for IO pins on top, bottom, left and right
48+
# each entry construct can be of one of the following
49+
# start <starting point for the following pin list>
50+
# pitch <pin ptich / spacing to use>
51+
# <pin>
52+
# <pin>
53+
array set pinGroups [list]
54+
set pinGroups(top) [list \
55+
"pitch [expr $m5pitch * 2]" \
56+
"start 500" \
57+
"io_debug_req" \
58+
"break 10" \
59+
"io_debug_resp" \
60+
"break 10" \
61+
"io_interrupts" \
62+
]
63+
64+
set pinGroups(left) [ list \
65+
"pitch [expr $m4pitch * 2]" \
66+
"start 200" \
67+
"reset" \
68+
"break 10" \
69+
"clock" \
70+
"break 10" \
71+
"io_l2_axi4_0_ar" \
72+
"break 10" \
73+
"io_l2_axi4_0_aw" \
74+
"break 10" \
75+
"io_l2_axi4_0_b" \
76+
"break 10" \
77+
"io_l2_axi4_0_r" \
78+
"break 10" \
79+
"io_l2_axi4_0_w" \
80+
]
81+
82+
set pinGroups(right) [ list \
83+
"pitch [expr $m4pitch * 2]" \
84+
"start 200" \
85+
"io_mem_axi4_0_ar" \
86+
"break 10" \
87+
"io_mem_axi4_0_aw" \
88+
"break 10" \
89+
"io_mem_axi4_0_b" \
90+
"break 10" \
91+
"io_mem_axi4_0_r" \
92+
"break 10" \
93+
"io_mem_axi4_0_w" \
94+
"break 50" \
95+
"io_mmio_axi4_0_ar" \
96+
"break 10" \
97+
"io_mmio_axi4_0_aw" \
98+
"break 10" \
99+
"io_mmio_axi4_0_b" \
100+
"break 10" \
101+
"io_mmio_axi4_0_r" \
102+
"break 10" \
103+
"io_mmio_axi4_0_w" \
104+
]
105+
106+
# process pin grouppings from instruction above
107+
# go thru each item in the pin grouping and issue
108+
# the ORFS constraint
109+
foreach side [array names pinGroups] {
110+
set pStart 0
111+
set pStop 0
112+
set pitch 0
113+
foreach ex $pinGroups($side) {
114+
if { [regexp {pitch (\S+)} $ex - number] } {
115+
set pitch $number
116+
continue
117+
}
118+
if { [regexp {start (\d+)} $ex - number] } {
119+
set pStart $number
120+
set pStop $number
121+
continue
122+
}
123+
if { [regexp {break (\d+)} $ex - number] } {
124+
set pStart [expr $pStart + $number]
125+
continue
126+
}
127+
set pins [match_pins ${ex}.*]
128+
set pStop [expr $pStart + (($pitch) * [llength $pins])]
129+
set_io_pin_constraint -region ${side}:${pStart}-${pStop} -pin_names $pins
130+
set pStart [expr $pStop + $pitch]
131+
}
132+
}
133+

‎flow/designs/asap7/megaboom/macro-placement.tcl‎

Lines changed: 72 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,72 @@
1+
# pre place all macro
2+
#
3+
set block [ord::get_db_block]
4+
set units [$block getDefUnits]
5+
6+
set coreArea [$block getCoreArea]
7+
set xMin [$coreArea xMin]
8+
set yMin [$coreArea yMin]
9+
10+
# macro pins on M4 starts with an offset of 0.012 from the bottom
11+
# of the macro; then, will need to adjust the placement of the macro
12+
# such that the pins will be on M4 grid
13+
set x $xMin
14+
set y [expr $yMin - int(0.012 * $units)]
15+
16+
# the algorithm is to place macro such what if 2 macros are side by side,
17+
# the macro should be flip alternately
18+
set orientList [list R0 MY]
19+
set flag 1
20+
foreach instName [list \
21+
coreplex/RocketTile/frontend/icache/_T_850/_T_850_ext/u_ram \
22+
coreplex/RocketTile/frontend/icache/_T_869/_T_850_ext/u_ram \
23+
coreplex/RocketTile/frontend/icache/_T_888/_T_850_ext/u_ram \
24+
coreplex/RocketTile/frontend/icache/_T_907/_T_850_ext/u_ram \
25+
coreplex/RocketTile/dcache/data/_T_118/_T_80_ext/u_ram_bank_0 \
26+
coreplex/RocketTile/dcache/data/_T_118/_T_80_ext/u_ram_bank_1 \
27+
coreplex/RocketTile/dcache/data/_T_215/_T_80_ext/u_ram_bank_0 \
28+
coreplex/RocketTile/dcache/data/_T_215/_T_80_ext/u_ram_bank_1 \
29+
coreplex/RocketTile/dcache/data/_T_253/_T_80_ext/u_ram_bank_0 \
30+
coreplex/RocketTile/dcache/data/_T_253/_T_80_ext/u_ram_bank_1 \
31+
coreplex/RocketTile/dcache/data/_T_80/_T_80_ext/u_ram_bank_0 \
32+
coreplex/RocketTile/dcache/data/_T_80/_T_80_ext/u_ram_bank_1 \
33+
coreplex/RocketTile/core/bpd_stage/br_predictor/counters/h_table/h_table/smem/smem_0_ext/u_regfile \
34+
coreplex/RocketTile/dcache/meta/_T_157/_T_157_ext/u_ram_bank_0 \
35+
coreplex/RocketTile/dcache/meta/_T_157/_T_157_ext/u_ram_bank_1 \
36+
coreplex/RocketTile/dcache/meta/_T_157/_T_157_ext/u_ram_bank_2 \
37+
coreplex/RocketTile/dcache/meta/_T_157/_T_157_ext/u_ram_bank_3 \
38+
coreplex/RocketTile/frontend/icache/tag_array/tag_array_ext/u_ram_bank_0 \
39+
coreplex/RocketTile/frontend/icache/tag_array/tag_array_ext/u_ram_bank_1 \
40+
coreplex/RocketTile/frontend/icache/tag_array/tag_array_ext/u_ram_bank_2 \
41+
coreplex/RocketTile/frontend/icache/tag_array/tag_array_ext/u_ram_bank_3 \
42+
coreplex/RocketTile/core/bpd_stage/br_predictor/counters/p_table/p_table_0/smem/u_smem_ext/u_regfile \
43+
coreplex/RocketTile/core/bpd_stage/br_predictor/counters/p_table/p_table_1/smem/u_smem_ext/u_regfile \
44+
coreplex/RocketTile/core/bpd_stage/br_predictor/brob/entries_info/u_entries_info_ext/u_regfile \
45+
] {
46+
set orient [lindex $orientList $flag]
47+
puts "====> instance $instName"
48+
set inst [$block findInst $instName]
49+
if {$inst == "NULL"} {
50+
puts "ERROR ====> instance $instName"
51+
}
52+
53+
set bbox [$inst getBBox]
54+
set w [$bbox getDX]
55+
set h [$bbox getDY]
56+
57+
set x [expr $x + ($flag * $w)]
58+
59+
$inst setPlacementStatus UNPLACE
60+
$inst setOrient $orient
61+
$inst setOrigin $x $y
62+
$inst setPlacementStatus FIRM
63+
64+
set x [expr $x + ([expr {! $flag}] * $w) + ((4 * $units) * ($flag + 1))]
65+
66+
set bx1 [expr $x + ($flag * $w)]
67+
set by1 [expr $x + ([expr {! $flag}] * $w)]
68+
set bx2 [expr $y]
69+
set by2 [expr $y + $h]
70+
71+
set flag [expr {! $flag}]
72+
}

‎flow/designs/asap7/megaboom/pdn.tcl‎

Lines changed: 43 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,43 @@
1+
####################################
2+
# global connections
3+
####################################
4+
add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power
5+
add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground
6+
7+
####################################
8+
# voltage domains
9+
####################################
10+
set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
11+
12+
####################################
13+
# standard cell grid
14+
####################################
15+
define_pdn_grid -name {top} -voltage_domains {CORE}
16+
add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins
17+
add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins
18+
19+
add_pdn_ring -grid {top} -layers {M6 M7} -widths {0.544 0.544} -spacings {0.5 0.5} -core_offset {0.144 0.144}
20+
add_pdn_ring -grid {top} -layers {M8 M9} -widths {0.544 0.544} -spacings {0.5 0.5} -core_offset {0.144 0.144}
21+
22+
add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.16} -offset {1.080} -extend_to_core_ring
23+
add_pdn_stripe -grid {top} -layer {M6} -width {0.16} -spacing {0.072} -pitch {2.16} -offset {1.080} -extend_to_core_ring
24+
25+
add_pdn_stripe -grid {top} -layer {M7} -width {0.288} -spacing {0.072} -pitch {4.32} -offset {3.156} -extend_to_core_ring
26+
add_pdn_stripe -grid {top} -layer {M8} -width {0.400} -spacing {0.072} -pitch {4.32} -offset {3.12} -extend_to_core_ring
27+
add_pdn_stripe -grid {top} -layer {M9} -width {0.400} -spacing {0.072} -pitch {4.32} -offset {3.100} -extend_to_core_ring
28+
29+
add_pdn_connect -grid {top} -layers {M1 M2}
30+
add_pdn_connect -grid {top} -layers {M2 M5}
31+
add_pdn_connect -grid {top} -layers {M5 M6}
32+
add_pdn_connect -grid {top} -layers {M6 M7}
33+
add_pdn_connect -grid {top} -layers {M7 M8}
34+
add_pdn_connect -grid {top} -layers {M8 M9}
35+
36+
####################################
37+
# macro grid
38+
####################################
39+
# The halo around the macro prevents pdn from blocking pin access
40+
define_pdn_grid -name {fakeram} -macro -cells {fake.*} -halo "3.0 3.0 3.0 3.0" -voltage_domains {CORE}
41+
add_pdn_connect -grid {fakeram} -layers {M4 M5}
42+
43+

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