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lines changed Original file line number Diff line number Diff line change @@ -280,6 +280,8 @@ configuration file.
280280- [ SYNTH_NETLIST_FILES] ( #SYNTH_NETLIST_FILES )
281281- [ SYNTH_OPT_HIER] ( #SYNTH_OPT_HIER )
282282- [ SYNTH_RETIME_MODULES] ( #SYNTH_RETIME_MODULES )
283+ - [ SYNTH_WRAPPED_ADDERS] ( #SYNTH_WRAPPED_ADDERS )
284+ - [ SYNTH_WRAPPED_MULTIPLIERS] ( #SYNTH_WRAPPED_MULTIPLIERS )
283285- [ TIEHI_CELL_AND_PORT] ( #TIEHI_CELL_AND_PORT )
284286- [ TIELO_CELL_AND_PORT] ( #TIELO_CELL_AND_PORT )
285287- [ VERILOG_DEFINES] ( #VERILOG_DEFINES )
@@ -452,8 +454,6 @@ configuration file.
452454
453455- [ OPENROAD_HIERARCHICAL] ( #OPENROAD_HIERARCHICAL )
454456- [ SWAP_ARITH_OPERATORS] ( #SWAP_ARITH_OPERATORS )
455- - [ SYNTH_WRAPPED_ADDERS] ( #SYNTH_WRAPPED_ADDERS )
456- - [ SYNTH_WRAPPED_MULTIPLIERS] ( #SYNTH_WRAPPED_MULTIPLIERS )
457457- [ SYNTH_WRAPPED_OPERATORS] ( #SYNTH_WRAPPED_OPERATORS )
458458
459459## generate_abstract variables
Original file line number Diff line number Diff line change @@ -303,13 +303,13 @@ SYNTH_WRAPPED_ADDERS:
303303 Specify the adder modules that can be used for synthesis, separated by commas.
304304 The default adder module is determined by the first element of this variable.
305305 stages :
306- - All stages
306+ - synth
307307SYNTH_WRAPPED_MULTIPLIERS :
308308 description : >
309309 Specify the multiplier modules that can be used for synthesis, separated by commas.
310310 The default multiplier module is determined by the first element of this variable.
311311 stages :
312- - All stages
312+ - synth
313313SWAP_ARITH_OPERATORS :
314314 description : >
315315 Improve timing QoR by swapping ALU and MULT arithmetic operators.
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