Merge pull request #2943 from Pinata-Consulting/synth-params-fix

Synth params fix

Author: maliberty

flow/designs/asap7/uart/config.mk

@@ -13,3 +13,4 @@ export TNS_END_PERCENT        = 100
 export EQUIVALENCE_CHECK     ?=   1
 export REMOVE_CELLS_FOR_EQY   = TAPCELL*
 export SKIP_GATE_CLONING      = 1
+export VERILOG_TOP_PARAMS = DATA_WIDTH 8

flow/scripts/synth_canonicalize.tcl

@@ -1,4 +1,10 @@
 source $::env(SCRIPTS_DIR)/synth_preamble.tcl
+
+dict for {key value} $::env(VERILOG_TOP_PARAMS) {
+  # Apply toplevel parameters
+  chparam -set $key $value $::env(DESIGN_NAME)
+}
+
 hierarchy -check -top $::env(DESIGN_NAME)
 # Get rid of unused modules
 opt_clean -purge

flow/scripts/synth_preamble.tcl

@@ -44,13 +44,6 @@ foreach file $::env(VERILOG_FILES) {
 
 source $::env(SCRIPTS_DIR)/synth_stdcells.tcl
 
-# Apply toplevel parameters (if exist)
-if {[env_var_exists_and_non_empty VERILOG_TOP_PARAMS]} {
-  dict for {key value} $::env(VERILOG_TOP_PARAMS) {
-    chparam -set $key $value $::env(DESIGN_NAME)
-  }
-}
-
 # Read platform specific mapfile for OPENROAD_CLKGATE cells
 if {[env_var_exists_and_non_empty CLKGATE_MAP_FILE]} {
   read_verilog -defer $::env(CLKGATE_MAP_FILE)

flow/scripts/variables.yaml

@@ -658,6 +658,7 @@ VERILOG_TOP_PARAMS:
     Apply toplevel params (if exist).
   stages:
     - synth
+  default: ""
 CORE_ASPECT_RATIO:
   description: >
     The core aspect ratio (height / width). This value is ignored if