updated asap7 cva6 memory sizes to remove tied off connections

Signed-off-by: Jeff Ng <[email protected]>

Author: jeffng-or

flow/designs/asap7/cva6/config.mk

@@ -65,17 +65,26 @@ export VERILOG_FILES          = $(sort $(wildcard $(SRC_HOME)/common/local/util/
 	$(SRC_HOME)/core/cvxif_example/include/cvxif_instr_pkg.sv \
 	$(sort $(wildcard $(SRC_HOME)/core/frontend/*.sv)) \
 	$(SRC_HOME)/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv \
-	$(PLATFORM_DIR)/verilog/fakeram7_256x256.sv
+	$(PLATFORM_DIR)/verilog/fakeram7_64x256.sv \
+	$(PLATFORM_DIR)/verilog/fakeram7_128x64.sv \
+	$(PLATFORM_DIR)/verilog/fakeram7_64x28.sv \
+	$(PLATFORM_DIR)/verilog/fakeram7_64x25.sv
 
 export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include \
 	$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu/src/common_cells/include \
 	$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cache_subsystem/hpdcache/rtl/include
 
 export VERILOG_DEFINES += -D HPDCACHE_ASSERT_OFF
 
-export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram7_256x256.lef
+export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram7_64x256.lef \
+			 $(PLATFORM_DIR)/lef/fakeram7_128x64.lef \
+			 $(PLATFORM_DIR)/lef/fakeram7_64x28.lef \
+			 $(PLATFORM_DIR)/lef/fakeram7_64x25.lef
 
-export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/fakeram7_256x256.lib
+export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/fakeram7_64x256.lib \
+			 $(PLATFORM_DIR)/lib/NLDM/fakeram7_128x64.lib \
+			 $(PLATFORM_DIR)/lib/NLDM/fakeram7_64x28.lib \
+			 $(PLATFORM_DIR)/lib/NLDM/fakeram7_64x25.lib
 
 export SDC_FILE               = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
 

flow/designs/src/cva6/README.md

@@ -1 +1,3 @@
 Extracted from https://github.com/openhwgroup/cva6
+
+Based on commit 3a389af with some changes for the RAMs

flow/designs/src/cva6/common/local/util/sram_cache.sv

@@ -52,7 +52,7 @@ module sram_cache #(
         rdata_o    = rdata_user[DATA_AND_USER_WIDTH-1:DATA_WIDTH];
         ruser_o    = rdata_user[USER_WIDTH-1:0];
       end
-       fakeram7_256x256 i_tc_sram_wrapper(
+       fakeram7_64x256 i_tc_sram_wrapper(
         .clk    ( clk_i                     ),
         .ce_in    ( req_i                     ),
         .we_in     ( we_i                      ),
@@ -91,7 +91,7 @@ module sram_cache #(
         rdata_o    = rdata_user;
         ruser_o    = '0;
       end
-       fakeram7_256x256 i_tc_sram_wrapper(
+       fakeram7_64x25 i_tc_sram_wrapper(
         .clk    ( clk_i                     ),
         .ce_in    ( req_i                     ),
         .we_in     ( we_i                      ),

flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv

@@ -39,7 +39,7 @@ module hpdcache_sram
     output logic [DATA_SIZE-1:0]  rdata
 );
 
-    fakeram7_256x256 ram_i (
+    fakeram7_64x28 ram_i (
         .clk(clk),
         .ce_in(cs),
         .we_in(we),

flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv

@@ -39,7 +39,7 @@ module hpdcache_sram_wbyteenable
     input  logic [DATA_SIZE/8-1:0] wbyteenable,
     output logic [DATA_SIZE-1:0]   rdata
 );
-   fakeram7_256x256 ram_i (
+   fakeram7_128x64 ram_i (
         .clk (clk),
         .ce_in(cs),
         .we_in(we),