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malibertymaliberty
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Merge pull request #3167 from eder-matheus/mpl_remove_manual_configs
remove manual configs for macro placer from public designs
2 parents 398e4e0 + 907b5c5 commit 926e4d8

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11 files changed

+6
-46
lines changed

11 files changed

+6
-46
lines changed

‎flow/designs/asap7/riscv32i/config.mk‎

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@@ -4,11 +4,6 @@ export PLATFORM = asap7
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export SYNTH_HIERARCHICAL ?= 1
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7-
export RTLMP_MIN_INST = 1000
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export RTLMP_MAX_INST = 3500
9-
export RTLMP_MIN_MACRO = 1
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export RTLMP_MAX_MACRO = 5
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export SYNTH_MINIMUM_KEEP_SIZE ?= 10000
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export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/riscv32i/*.v))

‎flow/designs/asap7/swerv_wrapper/BUILD.bazel‎

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@@ -100,10 +100,6 @@ orfs_flow(
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arguments = {
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"LIB_MODEL": "CCS",
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"SYNTH_HIERARCHICAL": "1",
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"RTLMP_MAX_INST": "30000",
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"RTLMP_MIN_INST": "5000",
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"RTLMP_MAX_MACRO": "30",
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"RTLMP_MIN_MACRO": "4",
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"DIE_AREA": "0 0 550 600",
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"CORE_AREA": "5 5 545 595",
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"PLACE_PINS_ARGS": "-exclude left:* -exclude right:*",

‎flow/designs/asap7/swerv_wrapper/config.mk‎

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@@ -42,12 +42,6 @@ export SYNTH_KEEP_MODULES ?= \
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ram_256x34
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# RTL_MP Settings
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export RTLMP_MAX_INST = 30000
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export RTLMP_MIN_INST = 5000
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export RTLMP_MAX_MACRO = 30
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export RTLMP_MIN_MACRO = 4
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export LIB_MODEL = CCS
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export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \

‎flow/designs/nangate45/ariane133/config.mk‎

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Original file line numberDiff line numberDiff line change
@@ -4,12 +4,6 @@ export PLATFORM = nangate45
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export SYNTH_HIERARCHICAL = 1
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7-
# RTL_MP Settings
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export RTLMP_MAX_INST = 30000
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export RTLMP_MIN_INST = 5000
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export RTLMP_MAX_MACRO = 16
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export RTLMP_MIN_MACRO = 4
12-
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export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ariane.sv2v.v \
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$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros.v
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‎flow/designs/nangate45/ariane136/config.mk‎

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Original file line numberDiff line numberDiff line change
@@ -5,10 +5,6 @@ export PLATFORM = nangate45
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export SYNTH_HIERARCHICAL = 1
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# RTL_MP Settings
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export RTLMP_MAX_INST = 30000
9-
export RTLMP_MIN_INST = 5000
10-
export RTLMP_MAX_MACRO = 16
11-
export RTLMP_MIN_MACRO = 4
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export RTLMP_SIGNATURE_NET_THRESHOLD = 30
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export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ariane.sv2v.v \

‎flow/designs/nangate45/ariane136/rules-base.json‎

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@@ -60,7 +60,7 @@
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"compare": "<="
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},
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"finish__timing__drv__hold_violation_count": {
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"value": 299,
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"value": 509,
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"compare": "<="
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},
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"finish__timing__wns_percent_delay": {

‎flow/designs/nangate45/black_parrot/config.mk‎

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Original file line numberDiff line numberDiff line change
@@ -4,11 +4,6 @@ export PLATFORM = nangate45
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export SYNTH_HIERARCHICAL = 1
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#
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# RTL_MP Settings
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export RTLMP_MAX_INST = 30000
9-
export RTLMP_MIN_INST = 5000
10-
export RTLMP_MAX_MACRO = 12
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export RTLMP_MIN_MACRO = 4
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export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \
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$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v

‎flow/designs/nangate45/bp_fe_top/config.mk‎

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Original file line numberDiff line numberDiff line change
@@ -4,11 +4,6 @@ export PLATFORM = nangate45
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export SYNTH_HIERARCHICAL = 1
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#
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# RTL_MP Settings
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export RTLMP_MAX_INST = 30000
9-
export RTLMP_MIN_INST = 5000
10-
export RTLMP_MAX_MACRO = 12
11-
export RTLMP_MIN_MACRO = 4
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export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \
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$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v
@@ -29,8 +24,8 @@ export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/io.tcl
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export MACRO_PLACE_HALO = 10 10
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export PLACE_DENSITY_LB_ADDON = 0.10
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export PLACE_DENSITY_MAX_POST_HOLD = 0.12
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export PLACE_DENSITY_LB_ADDON = 0.11
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export PLACE_DENSITY_MAX_POST_HOLD = 0.13
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export TNS_END_PERCENT = 100
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export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/fastroute.tcl

‎flow/designs/nangate45/bp_fe_top/rules-base.json‎

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@@ -32,7 +32,7 @@
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"compare": "<="
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},
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"detailedroute__route__wirelength": {
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"value": 2111490,
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"value": 2503735,
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"compare": "<="
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},
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"detailedroute__route__drc_errors": {
@@ -60,7 +60,7 @@
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"compare": "<="
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},
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"finish__timing__drv__hold_violation_count": {
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"value": 2500,
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"value": 100,
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"compare": "<="
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},
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"finish__timing__wns_percent_delay": {

‎flow/designs/nangate45/bp_multi_top/config.mk‎

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@@ -4,11 +4,6 @@ export PLATFORM = nangate45
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export SYNTH_HIERARCHICAL = 1
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#
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# RTL_MP Settings
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export RTLMP_MAX_INST = 30000
9-
export RTLMP_MIN_INST = 5000
10-
export RTLMP_MAX_MACRO = 12
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export RTLMP_MIN_MACRO = 4
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export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v \
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$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v

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