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Merge branch 'master' into secure-yosys0.49
2 parents c8ec904 + 87d2675 commit 93bb8fa

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4 files changed

+64
-22
lines changed

4 files changed

+64
-22
lines changed
Lines changed: 57 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,26 +1,68 @@
1+
source $::env(SCRIPTS_DIR)/util.tcl
2+
13
foreach libFile $::env(LIB_FILES) {
24
if {[lsearch -exact $::env(ADDITIONAL_LIBS) $libFile] == -1} {
35
read_liberty $libFile
46
}
57
}
68

7-
read_verilog results/asap7/mock-array_Element/base/6_final.v
8-
read_verilog $::env(RESULTS_DIR)/6_final.v
9-
read_verilog $::env(PLATFORM_DIR)/verilog/stdcell/empty.v
10-
11-
link_design MockArray
9+
log_cmd read_verilog results/asap7/mock-array_Element/base/6_final.v
10+
log_cmd read_verilog $::env(RESULTS_DIR)/6_final.v
11+
log_cmd read_verilog $::env(PLATFORM_DIR)/verilog/stdcell/empty.v
12+
log_cmd link_design MockArray
1213

13-
read_sdc $::env(RESULTS_DIR)/6_final.sdc
14-
read_spef $::env(RESULTS_DIR)/6_final.spef
14+
log_cmd read_sdc $::env(RESULTS_DIR)/6_final.sdc
15+
log_cmd read_spef $::env(RESULTS_DIR)/6_final.spef
16+
puts "read_spef for ces_*_* macros"
1517
for {set x 0} {$x < 8} {incr x} {
1618
for {set y 0} {$y < 8} {incr y} {
1719
read_spef -path ces_${x}_${y} results/asap7/mock-array_Element/base/6_final.spef
1820
}
1921
}
2022

21-
report_parasitic_annotation
22-
report_power
23-
read_vcd -scope TOP/MockArray $::env(RESULTS_DIR)/MockArrayTestbench.vcd
23+
log_cmd report_power
24+
25+
set vcd_file $::env(RESULTS_DIR)/MockArrayTestbench.vcd
26+
log_cmd read_vcd -scope TOP/MockArray $vcd_file
27+
28+
puts "Total number of pins to be annotated: [llength [get_pins -hierarchical *]]"
29+
set no_vcd_activity {}
30+
set pins [get_pins -hierarchical *]
31+
foreach pin $pins {
32+
set activity [get_property $pin activity]
33+
set activity_origin [lindex $activity 2]
34+
if {$activity_origin == "vcd"} {
35+
continue
36+
}
37+
if {$activity_origin == "constant"} {
38+
continue
39+
}
40+
if {$activity_origin == "unknown"} {
41+
continue
42+
}
43+
if {[get_property $pin is_hierarchical]} {
44+
continue
45+
}
46+
if {$activity_origin == "clock"} {
47+
continue
48+
}
49+
set direction [get_property $pin direction]
50+
if {$direction == "internal"} {
51+
continue
52+
}
53+
lappend no_vcd_activity "[get_full_name $pin] $activity $direction"
54+
if {[llength $no_vcd_activity] >= 10} {
55+
break
56+
}
57+
}
58+
59+
if {[llength $no_vcd_activity] > 0} {
60+
puts "Error: Listing [llength $no_vcd_activity] pins without activity from $vcd_file:"
61+
foreach pin $no_vcd_activity {
62+
puts $pin
63+
}
64+
exit 1
65+
}
2466

2567
set ces {}
2668
for {set x 0} {$x < 8} {incr x} {
@@ -29,5 +71,9 @@ for {set x 0} {$x < 8} {incr x} {
2971
}
3072
}
3173

74+
puts {report_power -instances [get_cells $ces]}
3275
report_power -instances [get_cells $ces]
33-
report_power
76+
log_cmd report_power
77+
78+
log_cmd report_parasitic_annotation
79+
log_cmd report_activity_annotation -report_unannotated

flow/designs/asap7/mock-array/simulate.sh

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -22,8 +22,6 @@ verilator -Wall --cc \
2222
-Wno-DECLFILENAME \
2323
-Wno-UNUSEDSIGNAL \
2424
-Wno-PINMISSING \
25-
--coverage-toggle \
26-
--coverage-underscore \
2725
--Mdir $OBJ_DIR \
2826
--top-module MockArray \
2927
--trace \
@@ -33,8 +31,8 @@ verilator -Wall --cc \
3331
$PLATFORM_DIR/verilog/stdcell/asap7sc7p5t_SIMPLE_RVT_TT_201020.v \
3432
$PLATFORM_DIR/verilog/stdcell/dff.v \
3533
$PLATFORM_DIR/verilog/stdcell/empty.v \
36-
$POST_DIR/MockArrayFinal.v \
37-
$POST_DIR/MockArrayElement.v \
34+
$FLOW_HOME/results/asap7/mock-array/base/6_final.v \
35+
$FLOW_HOME/results/asap7/mock-array_Element/base/6_final.v \
3836
--exe \
3937
$FLOW_HOME/designs/src/mock-array/simulate.cpp
4038

@@ -43,4 +41,3 @@ make -j16 -C $OBJ_DIR -f VMockArray.mk
4341

4442
# Run the simulation
4543
$OBJ_DIR/VMockArray
46-
verilator_coverage $RESULTS_DIR/coverage.dat --annotate $REPORTS_DIR/

flow/designs/src/mock-array/simulate.cpp

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -89,9 +89,6 @@ int main(int argc, char** argv) {
8989
vcd->flush();
9090
vcd->close();
9191

92-
std::string coverage_file = std::string(getenv("RESULTS_DIR")) + "/coverage.dat";
93-
Verilated::threadContextp()->coveragep()->write(coverage_file.c_str());
94-
9592
top->final();
9693
delete top;
9794
return 0;

flow/scripts/util.tcl

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,15 @@
11
proc log_cmd {cmd args} {
22
# log the command, escape arguments with spaces
3-
puts -nonewline "$cmd[join [lmap arg $args {expr {[string match {* *} $arg] ? " \"$arg\"" : " $arg"}}] ""]"
3+
set log_cmd "$cmd[join [lmap arg $args {format " %s" [expr {[string match {* *} $arg] ? "\"$arg\"" : "$arg"}]}] ""]"
4+
puts $log_cmd
45
set start [clock seconds]
56
$cmd {*}$args
67
set time [expr {[clock seconds] - $start}]
78
if {$time >= 5} {
8-
puts -nonewline " ($time seconds)"
9+
# Ideally we'd use a single line, but the command can output text
10+
# and we don't want to mix it with the log, so output the time it took afterwards.
11+
puts "Took $time seconds: $log_cmd"
912
}
10-
puts ""
1113
}
1214

1315
proc fast_route {} {

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