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- CHANGELOG+3
- Makefile+2-2
- backends/aiger/xaiger.cc+22
- backends/cxxrtl/cxxrtl_backend.cc+1-1
- docs/source/cell/word_arith.rst+1-1
- docs/source/code_examples/fifo/fifo.ys+1-1
- docs/source/conf.py+3
- docs/source/getting_started/example_synth.rst+1-1
- frontends/verific/verific.cc+7-3
- frontends/verilog/verilog_frontend.cc+87
- kernel/celledges.cc+1-1
- kernel/celltypes.h+1
- kernel/consteval.h+1-1
- kernel/constids.inc+8
- kernel/fmt.cc+5-4
- kernel/macc.h+112-36
- kernel/rtlil.cc+45
- kernel/rtlil.h+2
- kernel/satgen.cc+1-1
- passes/cmds/splitcells.cc+1-2
- passes/opt/share.cc+41-3
- passes/techmap/booth.cc+1-1
- passes/techmap/maccmap.cc+1-1
- passes/techmap/techmap.cc+4-4
- techlibs/common/simlib.v+114
- techlibs/common/techmap.v+10-3
- techlibs/gowin/cells_sim.v+1-1
- tests/alumacc/basic.ys+61
- tests/alumacc/macc_infer_n_unmap.ys+19
- tests/various/bug4909.ys+44
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