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Merge pull request #2629 from povik/wrapped-operators
Wrapped operators synthesis flow
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‎docs/user/FlowVariables.md‎

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@@ -184,6 +184,7 @@ configuration file.
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| <a name="SYNTH_HIERARCHICAL"></a>SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0| |
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| <a name="SYNTH_MEMORY_MAX_BITS"></a>SYNTH_MEMORY_MAX_BITS| Maximum number of bits for memory synthesis.| 4096| |
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| <a name="SYNTH_NETLIST_FILES"></a>SYNTH_NETLIST_FILES| Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.| | |
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| <a name="SYNTH_WRAPPED_OPERATORS"></a>SYNTH_WRAPPED_OPERATORS| Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.| | |
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| <a name="TAPCELL_TCL"></a>TAPCELL_TCL| Path to Endcap and Welltie cells file.| | |
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| <a name="TAP_CELL_NAME"></a>TAP_CELL_NAME| Name of the cell to use in tap cell insertion.| | |
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| <a name="TECH_LEF"></a>TECH_LEF| A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.| | |
@@ -213,6 +214,7 @@ configuration file.
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- [SYNTH_HIERARCHICAL](#SYNTH_HIERARCHICAL)
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- [SYNTH_MEMORY_MAX_BITS](#SYNTH_MEMORY_MAX_BITS)
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- [SYNTH_NETLIST_FILES](#SYNTH_NETLIST_FILES)
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- [SYNTH_WRAPPED_OPERATORS](#SYNTH_WRAPPED_OPERATORS)
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- [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
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- [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)
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- [VERILOG_FILES](#VERILOG_FILES)

‎flow/scripts/abc_speed_gia_only.script‎

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&st
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&dch
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&nf
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&st
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&syn2
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&if -g -K 6
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&synch2
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&nf
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&st
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&syn2
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&if -g -K 6
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&synch2
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&nf
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&st
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&syn2
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&if -g -K 6
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&synch2
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&nf
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&st
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&syn2
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&if -g -K 6
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&synch2
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&nf
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&st
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&syn2
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&if -g -K 6
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&synch2
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&nf

‎flow/scripts/synth.tcl‎

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@@ -34,7 +34,13 @@ if {![env_var_equals SYNTH_HIERARCHICAL 1]} {
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json -o $::env(RESULTS_DIR)/mem.json
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# Run report and check here so as to fail early if this synthesis run is doomed
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exec -- python3 $::env(SCRIPTS_DIR)/mem_dump.py --max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/mem.json
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synth -top $::env(DESIGN_NAME) -run fine: {*}$::env(SYNTH_FULL_ARGS)
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if {![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS]} {
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synth -top $::env(DESIGN_NAME) -run fine: {*}$::env(SYNTH_FULL_ARGS)
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} else {
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source $::env(SCRIPTS_DIR)/synth_wrap_operators.tcl
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}
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# Get rid of indigestibles
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chformal -remove
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@@ -76,7 +82,15 @@ if {[env_var_exists_and_non_empty DFF_LIB_FILE]} {
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}
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opt
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log_cmd abc {*}$abc_args
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if {![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS]} {
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log_cmd abc {*}$abc_args
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} else {
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scratchpad -set abc9.script scripts/abc_speed_gia_only.script
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# crop out -script from arguments
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set abc_args [lrange $abc_args 2 end]
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log_cmd abc_new {*}$abc_args
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delete {t:$specify*}
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}
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# Replace undef values with defined constants
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setundef -zero
@@ -101,10 +115,17 @@ tee -o $::env(REPORTS_DIR)/synth_check.txt check
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tee -o $::env(REPORTS_DIR)/synth_stat.txt stat {*}$stat_libs
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# check the design is composed exclusively of target cells, and check for other problems
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check -assert -mapped
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if {![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS]} {
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check -assert -mapped
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} else {
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# Wrapped operator synthesis leaves around $buf cells which `check -mapped`
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# gets confused by, once Yosys#4931 is merged we can remove this branch and
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# always run `check -assert -mapped`
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check -assert
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}
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# Write synthesized design
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write_verilog -noexpr -nohex -nodec $::env(RESULTS_DIR)/1_1_yosys.v
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write_verilog -nohex -nodec $::env(RESULTS_DIR)/1_1_yosys.v
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# One day a more sophisticated synthesis will write out a modified
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# .sdc file after synthesis. For now, just copy the input .sdc file,
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# making synthesis more consistent with other stages.

‎flow/scripts/synth_wrap_operators-booth.v‎

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(* techmap_wrap = "booth" *)
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(* techmap_celltype = "$macc" *)
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module _70_macc;
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endmodule

‎flow/scripts/synth_wrap_operators.tcl‎

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set deferred_cells {
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{
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\$alu
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ALU_{A_WIDTH}_{A_SIGNED}_{B_WIDTH}_{B_SIGNED}_{Y_WIDTH}{%unused}
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{HAN_CARLSON -map +/choices/han-carlson.v}
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{KOGGE_STONE -map +/choices/kogge-stone.v}
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{SKLANSKY -map +/choices/sklansky.v}
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{BRENT_KUNG}
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}
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{
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\$macc
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MACC_{CONFIG}_{Y_WIDTH}{%unused}
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{BASE -map +/choices/han-carlson.v}
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{BOOTH -max_iter 1 -map ../flow/scripts/synth_wrap_operators-booth.v}
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}
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}
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techmap {*}[join [lmap cell $deferred_cells {string cat "-dont_map [lindex $cell 0]"}] " "]
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foreach info $deferred_cells {
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set type [lindex $info 0]
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set naming_template [lindex $info 1]
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# default architecture and its suffix
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set default [lindex $info 2]
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set default_suffix [lindex $default 0]
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log -header "Generating architectural options for $type"
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log -push
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wrapcell \
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-setattr arithmetic_operator \
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-setattr copy_pending \
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-formatattr implements_operator $naming_template \
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-formatattr architecture $default_suffix \
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-formatattr source_cell $type \
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-name ${naming_template}_${default_suffix} \
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t:$type r:A_WIDTH>=10 r:Y_WIDTH>=14 %i %i
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# make per-architecture copies of the unmapped module
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foreach modname [tee -q -s result.string select -list-mod A:arithmetic_operator A:copy_pending %i] {
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setattr -mod -unset copy_pending $modname
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# iterate over non-default architectures
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foreach arch [lrange $info 3 end] {
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set suffix [lindex $arch 0]
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set base [rtlil::get_attr -string -mod $modname implements_operator]
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set newname ${base}_${suffix}
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yosys copy $modname $newname
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yosys setattr -mod -set architecture \"$suffix\" $newname
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}
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}
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# iterate over all architectures, both the default and non-default
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foreach arch [lrange $info 2 end] {
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set suffix [lindex $arch 0]
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set extra_map_args [lrange $arch 1 end]
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# map all operator copies which were selected to have this architecture
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techmap -map +/techmap.v {*}$extra_map_args A:source_cell=$type A:architecture=$suffix %i
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# booth isn't able to map all $macc configurations: catch if this is one
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# of those and delete the option
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delete A:source_cell=$type A:architecture=$suffix %i t:\$macc %m %i
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}
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log -pop
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}
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opt -fast -full
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memory_map
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opt -full
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# Get rid of indigestibles
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chformal -remove
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setattr -mod -set abc9_script {"+&dch;&nf -R 5;"} A:arithmetic_operator
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setattr -mod -set abc9_box 1 A:arithmetic_operator
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techmap -map +/techmap.v -map +/choices/han-carlson.v

‎flow/scripts/variables.yaml‎

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@@ -239,6 +239,13 @@ MAX_UNGROUP_SIZE:
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platform's standard cell library. The default value is platform specific.
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stages:
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- synth
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SYNTH_WRAPPED_OPERATORS:
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description: >
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Synthesize multiple architectural options for each arithmetic operator in the
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design. These options are available for switching among in later stages of
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the flow.
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stages:
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- synth
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FLOORPLAN_DEF:
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description: |
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Use the DEF file to initialize floorplan.

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