Merge branch 'master' into secure-gf12-bps-incr-density

Author: eder-matheus

flow/Makefile

@@ -1069,7 +1069,7 @@ klayout:
 
 .phony: run
 run:
-	$(OPENROAD_CMD) -no_splash $(RUN_SCRIPT)
+	$(OPENROAD_CMD) -no_splash $(if $(filter %.py,$(RUN_SCRIPT)),-python) $(RUN_SCRIPT)
 
 # Utilities
 #-------------------------------------------------------------------------------

flow/designs/asap7/aes-block/metadata-base-ok.json

@@ -8,7 +8,7 @@
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 7333,
+        "value": 7332,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
@@ -24,7 +24,7 @@
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
-        "value": 1075,
+        "value": 1262,
         "compare": "<="
     },
     "globalroute__antenna_diodes_count": {
@@ -48,7 +48,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -236.72,
+        "value": -227.71,
         "compare": ">="
     },
     "finish__design__instance__area": {
@@ -60,11 +60,11 @@
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {
-        "value": 331,
+        "value": 248,
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -45.84,
+        "value": -44.5,
         "compare": ">="
     }
 }

flow/designs/asap7/aes-block/rules-base.json

@@ -21,15 +21,30 @@ set_clock_groups -group $clk1_name -group $clk2_name -asynchronous -allow_paths
 set_false_path -from [get_ports *rst_n]
 set_false_path -to [get_ports *rst_n]
 
-# Give the world outside of the FIFO time to operate
-# on the cycle it is reading/writiing to the FIFO
-set min_percent 0.1
-set max_percent 0.5
-
-set_input_delay -clock $clk2_name -max [expr $clk2_period * $max_percent] [match_pins .* input 0]
-set_output_delay -clock $clk2_name -max [expr $clk2_period * $max_percent] [match_pins .* output 0]
-set_input_delay -clock $clk2_name -min [expr $clk2_period * $min_percent] [match_pins .* input 0]
-set_output_delay -clock $clk2_name -min [expr $clk2_period * $min_percent] [match_pins .* output 0]
+# The mock-cpu is a macro connecting to a slower peripheral bus and possibly DRAM.
+# Avoid using set_input/output_delay here.
+# Register-to-register paths are checked at the mock-cpu level or from the mock-cpu
+# .lib file to an external register.
+# Timing closure is ensured at the SoC level where the mock-cpu is connected.
+# Instead, set strict optimization targets for inputs and outputs to ensure
+# constraints are not too loose.
+set non_clk_inputs {}
+set clock_ports [list [get_ports $clk1_name] [get_ports $clk2_name]]
+foreach input [all_inputs] {
+  if {[lsearch -exact $clock_ports $input] == -1} {
+    lappend non_clk_inputs $input
+  }
+}
+
+set_max_delay 80 -from $non_clk_inputs -to [all_outputs]
+group_path -name in2out -from $non_clk_inputs -to [all_outputs]
+
+set all_register_outputs [get_pins -of_objects [all_registers] -filter {direction == output}]
+set_max_delay 80 -from $non_clk_inputs -to [all_registers]
+set_max_delay 80 -from $all_register_outputs -to [all_outputs]
+group_path -name in2reg -from $non_clk_inputs -to [all_registers]
+group_path -name reg2out -from [all_registers] -to [all_outputs]
+group_path -name reg2reg -from [all_registers] -to [all_registers]
 
 ## Dual clock fifo timing constraints
 # Using fastest clock as constaint