synth: apply VERILOG_TOP_PARAMS during canonicalization

Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

flow/scripts/synth_canonicalize.tcl

@@ -1,4 +1,12 @@
 source $::env(SCRIPTS_DIR)/synth_preamble.tcl
+
+# Apply toplevel parameters (if exist)
+if {[env_var_exists_and_non_empty VERILOG_TOP_PARAMS]} {
+  dict for {key value} $::env(VERILOG_TOP_PARAMS) {
+    chparam -set $key $value $::env(DESIGN_NAME)
+  }
+}
+
 hierarchy -check -top $::env(DESIGN_NAME)
 # Get rid of unused modules
 opt_clean -purge

flow/scripts/synth_preamble.tcl

@@ -44,13 +44,6 @@ foreach file $::env(VERILOG_FILES) {
 
 source $::env(SCRIPTS_DIR)/synth_stdcells.tcl
 
-# Apply toplevel parameters (if exist)
-if {[env_var_exists_and_non_empty VERILOG_TOP_PARAMS]} {
-  dict for {key value} $::env(VERILOG_TOP_PARAMS) {
-    chparam -set $key $value $::env(DESIGN_NAME)
-  }
-}
-
 # Read platform specific mapfile for OPENROAD_CLKGATE cells
 if {[env_var_exists_and_non_empty CLKGATE_MAP_FILE]} {
   read_verilog -defer $::env(CLKGATE_MAP_FILE)