Merge pull request #1154 from Pinata-Consulting/mock-array-rename

mock-array: renamed mock-array-big to mock-array

Author: maliberty

flow/Makefile

@@ -76,7 +76,7 @@
 # DESIGN_CONFIG=./designs/asap7/ibex/config.mk
 # DESIGN_CONFIG=./designs/asap7/jpeg/config.mk
 # DESIGN_CONFIG=./designs/asap7/megaboom/config.mk
-# DESIGN_CONFIG=./designs/asap7/mock-array-big/config.mk
+# DESIGN_CONFIG=./designs/asap7/mock-array/config.mk
 # DESIGN_CONFIG=./designs/asap7/riscv32i/config.mk
 # DESIGN_CONFIG=./designs/asap7/sha3/config.mk
 # DESIGN_CONFIG=./designs/asap7/swerv_wrapper/config.mk

…s/asap7/mock-array-big/Element/config.mk …signs/asap7/mock-array/Element/config.mkflow/designs/asap7/mock-array-big/Element/config.mk renamed to flow/designs/asap7/mock-array/Element/config.mk flow/designs/asap7/mock-array-big/Element/config.mk renamed to flow/designs/asap7/mock-array/Element/config.mk

@@ -1,10 +1,10 @@
-include designs/asap7/mock-array-big/defaults.mk
+include designs/asap7/mock-array/defaults.mk
 
 export DESIGN_NAME = Element
-export DESIGN_NICKNAME = mock-array-big_Element
+export DESIGN_NICKNAME = mock-array_Element
 
-export VERILOG_FILES = designs/src/mock-array-big/*.v
-export SDC_FILE      = designs/asap7/mock-array-big/Element/constraints.sdc
+export VERILOG_FILES = designs/src/mock-array/*.v
+export SDC_FILE      = designs/asap7/mock-array/Element/constraints.sdc
 
 export PLATFORM               = asap7
 
@@ -16,18 +16,18 @@ export CORE_AREA = $(shell \
  export MOCK_ARRAY_HEIGHT=$(MOCK_ARRAY_HEIGHT) && \
  export MOCK_ARRAY_WIDTH=$(MOCK_ARRAY_WIDTH) && \
  export MOCK_ARRAY_PITCH_SCALE=$(MOCK_ARRAY_PITCH_SCALE) && \
- cd designs/asap7/mock-array-big && \
+ cd designs/asap7/mock-array && \
  python3 -c "import config; print(f'{config.ce_margin_x} {config.ce_margin_y} {config.ce_width - config.ce_margin_x} {config.ce_height - config.ce_margin_y}')")
 export DIE_AREA = $(shell \
  export MOCK_ARRAY_HEIGHT=$(MOCK_ARRAY_HEIGHT) && \
  export MOCK_ARRAY_WIDTH=$(MOCK_ARRAY_WIDTH) && \
  export MOCK_ARRAY_PITCH_SCALE=$(MOCK_ARRAY_PITCH_SCALE) && \
- cd designs/asap7/mock-array-big && \
+ cd designs/asap7/mock-array && \
  python3 -c "import config; print(f'0 0 {config.ce_width} {config.ce_height}')")
 
-export IO_CONSTRAINTS = designs/asap7/mock-array-big/Element/io.tcl
+export IO_CONSTRAINTS = designs/asap7/mock-array/Element/io.tcl
 
-export PDN_TCL = designs/asap7/mock-array-big/Element/pdn.tcl
+export PDN_TCL = designs/asap7/mock-array/Element/pdn.tcl
 
 # max routing layer need to be set to M5, since M6 is needed for next level up to connect
 # to the ring and stipe

…7/mock-array-big/Element/constraints.sdc …asap7/mock-array/Element/constraints.sdcflow/designs/asap7/mock-array-big/Element/constraints.sdc renamed to flow/designs/asap7/mock-array/Element/constraints.sdc flow/designs/asap7/mock-array-big/Element/constraints.sdc renamed to flow/designs/asap7/mock-array/Element/constraints.sdc

@@ -1,4 +1,4 @@
-source designs/asap7/mock-array-big/util.tcl
+source designs/asap7/mock-array/util.tcl
 
 set assignments [list \
     top bottom \

…igns/asap7/mock-array-big/Element/io.tcl …/designs/asap7/mock-array/Element/io.tclflow/designs/asap7/mock-array-big/Element/io.tcl renamed to flow/designs/asap7/mock-array/Element/io.tcl flow/designs/asap7/mock-array-big/Element/io.tcl renamed to flow/designs/asap7/mock-array/Element/io.tcl

@@ -18,10 +18,10 @@ export FLOW_VARIANT=small
 #export MOCK_ARRAY_HEIGHT=16
 #export MOCK_ARRAY_DATAWIDTH=64
 #export FLOW_VARIANT=giant
-export DESIGN_CONFIG=designs/asap7/mock-array-big/config.mk
+export DESIGN_CONFIG=designs/asap7/mock-array/config.mk
 ```
 
-Now run configure, which a custom target in mock-array-big, that runs Chisel to
+Now run configure, which a custom target in mock-array, that runs Chisel to
 regenerate the Verilog code for the above configuration:
 
 ```
@@ -39,10 +39,10 @@ Element/constraint.sdc
 
 A relatively simple constraint.sdc is adequate for the Element as
 timing is exported when the Element macro is made and checked at the
-mock-array-big level.
+mock-array level.
 
 Note that a failure on timing at the Element level is
-not a problem, as long as timing is met at the mock-array-big level.
+not a problem, as long as timing is met at the mock-array level.
 
 The purpose of the constraint.sdc file at the Element level is to
 be able to iterate on the Element during development and work on,
@@ -56,7 +56,7 @@ Optimizing Element/constraint.sdc
 Before considering the various strategies to articulate an Element/constraint.sdc
 file below, note that no tests have been run to verify that these
 different constraint.sdc changes below have any effects on the quality
-of results at the mock-array-big level. If there are no substantial
+of results at the mock-array level. If there are no substantial
 differences in quality of results and timing is met, then the differences
 between the strategies below are inconsequential.
 

…gns/asap7/mock-array-big/Element/pdn.tcl …designs/asap7/mock-array/Element/pdn.tclflow/designs/asap7/mock-array-big/Element/pdn.tcl renamed to flow/designs/asap7/mock-array/Element/pdn.tcl flow/designs/asap7/mock-array-big/Element/pdn.tcl renamed to flow/designs/asap7/mock-array/Element/pdn.tcl

@@ -1,12 +1,12 @@
-include designs/asap7/mock-array-big/defaults.mk
+include designs/asap7/mock-array/defaults.mk
 
 export DESIGN_NAME = MockArray
-export DESIGN_NICKNAME = mock-array-big
+export DESIGN_NICKNAME = mock-array
 
-export VERILOG_FILES_BLACKBOX = designs/src/mock-array-big/Element.v
-export VERILOG_FILES = designs/src/mock-array-big/*.v
+export VERILOG_FILES_BLACKBOX = designs/src/mock-array/Element.v
+export VERILOG_FILES = designs/src/mock-array/*.v
 
-export SDC_FILE      = designs/asap7/mock-array-big/constraints.sdc
+export SDC_FILE      = designs/asap7/mock-array/constraints.sdc
 
 export PLATFORM               = asap7
 
@@ -16,30 +16,30 @@ export CORE_AREA = $(shell \
  export MOCK_ARRAY_HEIGHT=$(MOCK_ARRAY_HEIGHT) && \
  export MOCK_ARRAY_WIDTH=$(MOCK_ARRAY_WIDTH) && \
  export MOCK_ARRAY_PITCH_SCALE=$(MOCK_ARRAY_PITCH_SCALE) && \
- cd designs/asap7/mock-array-big && \
+ cd designs/asap7/mock-array && \
  python3 -c "import config; print(f'{config.margin_x} {config.margin_y} {config.core_width + config.margin_x} {config.core_height + config.margin_y}')")
 export DIE_AREA = $(shell \
  export MOCK_ARRAY_HEIGHT=$(MOCK_ARRAY_HEIGHT) && \
  export MOCK_ARRAY_WIDTH=$(MOCK_ARRAY_WIDTH) && \
  export MOCK_ARRAY_PITCH_SCALE=$(MOCK_ARRAY_PITCH_SCALE) && \
- cd designs/asap7/mock-array-big && \
+ cd designs/asap7/mock-array && \
  python3 -c "import config; print(f'0 0 {config.die_width} {config.die_height}')")
 
 BLOCKS = Element
 
 export GDS_ALLOW_EMPTY = Element
 
-export MACRO_PLACEMENT_TCL = ./designs/asap7/mock-array-big/macro-placement.tcl
+export MACRO_PLACEMENT_TCL = ./designs/asap7/mock-array/macro-placement.tcl
 
-export IO_CONSTRAINTS = designs/asap7/mock-array-big/io.tcl
+export IO_CONSTRAINTS = designs/asap7/mock-array/io.tcl
 
-export PDN_TCL = designs/asap7/mock-array-big/pdn.tcl
+export PDN_TCL = designs/asap7/mock-array/pdn.tcl
 export TNS_END_PERCENT       = 100
 
 # Target to force generation of Verilog per user settings
 #   MOCK_ARRAY_WIDTH and MOCK_ARRAY_HEIGHT
 verilog:
-	./designs/asap7/mock-array-big/verilog.sh
+	./designs/asap7/mock-array/verilog.sh
 
 # If this design isn't quickly done in detailed routing, something is wrong.
 # At time of adding this option, only 12 iterations were needed for 0