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1 parent 8e36a08 commit 9a0bdedCopy full SHA for 9a0bded
flow/designs/asap7/mock-array/config.mk
@@ -32,7 +32,7 @@ export MACRO_PLACEMENT_TCL = ./designs/asap7/mock-array/macro-placement.tcl
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export IO_CONSTRAINTS = designs/asap7/mock-array/io.tcl
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-export PDN_TCL = designs/asap7/mock-array/pdn.tcl
+export PDN_TCL = $(FLOW_HOME)/platforms/asap7/openRoad/pdn/BLOCKS_grid_strategy.tcl
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# Target to force generation of Verilog per user settings MOCK_ARRAY_TABLE (rows, cols)
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verilog:
flow/designs/asap7/mock-array/pdn.tcl
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