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uart-no-param: simple Verilog without parameters to create simple macro tests
VERILOG_TOP_PARAMS does not work in conjunction with the BLOCKS makefile variable. This is a simple code-base suitable for non-trivial smoke-tests on e.g. ASAP7 Signed-off-by: Øyvind Harboe <[email protected]>
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‎flow/designs/src/uart-no-param/LICENSE‎

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/*
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Copyright (c) 2014-2017 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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‎flow/designs/src/uart-no-param/README.md‎

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# Summary
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Basic Universal Asynchronous Receiver Transmitter, communications application
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# Source
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# Modifications
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- Added sdc timing constraints.
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- Added LICENSE file.

‎flow/designs/src/uart-no-param/uart.v‎

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/*
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Copyright (c) 2014-2017 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream UART
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*/
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module uart(
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input wire clk,
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input wire rst,
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/*
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* AXI input
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*/
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input wire [8-1:0] s_axis_tdata,
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input wire s_axis_tvalid,
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output wire s_axis_tready,
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/*
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* AXI output
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*/
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output wire [8-1:0] m_axis_tdata,
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output wire m_axis_tvalid,
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input wire m_axis_tready,
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/*
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* UART interface
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*/
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input wire rxd,
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output wire txd,
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/*
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* Status
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*/
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output wire tx_busy,
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output wire rx_busy,
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output wire rx_overrun_error,
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output wire rx_frame_error,
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/*
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* Configuration
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*/
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input wire [15:0] prescale
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);
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uart_tx uart_tx_inst (
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.clk(clk),
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.rst(rst),
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// axi input
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.s_axis_tdata(s_axis_tdata),
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.s_axis_tvalid(s_axis_tvalid),
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.s_axis_tready(s_axis_tready),
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// output
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.txd(txd),
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// status
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.busy(tx_busy),
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// configuration
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.prescale(prescale)
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);
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uart_rx uart_rx_inst (
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.clk(clk),
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.rst(rst),
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// axi output
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.m_axis_tdata(m_axis_tdata),
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.m_axis_tvalid(m_axis_tvalid),
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.m_axis_tready(m_axis_tready),
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// input
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.rxd(rxd),
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// status
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.busy(rx_busy),
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.overrun_error(rx_overrun_error),
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.frame_error(rx_frame_error),
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// configuration
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.prescale(prescale)
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);
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endmodule

‎flow/designs/src/uart-no-param/uart_rx.v‎

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/*
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Copyright (c) 2014-2017 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9+
copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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12+
The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream UART
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*/
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module uart_rx(
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input wire clk,
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input wire rst,
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/*
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* AXI output
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*/
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output wire [8-1:0] m_axis_tdata,
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output wire m_axis_tvalid,
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input wire m_axis_tready,
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/*
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* UART interface
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*/
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input wire rxd,
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/*
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* Status
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*/
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output wire busy,
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output wire overrun_error,
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output wire frame_error,
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/*
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* Configuration
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*/
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input wire [15:0] prescale
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);
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reg [8-1:0] m_axis_tdata_reg = 0;
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reg m_axis_tvalid_reg = 0;
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reg rxd_reg = 1;
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reg busy_reg = 0;
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reg overrun_error_reg = 0;
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reg frame_error_reg = 0;
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reg [8-1:0] data_reg = 0;
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reg [18:0] prescale_reg = 0;
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reg [3:0] bit_cnt = 0;
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assign m_axis_tdata = m_axis_tdata_reg;
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assign m_axis_tvalid = m_axis_tvalid_reg;
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assign busy = busy_reg;
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assign overrun_error = overrun_error_reg;
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assign frame_error = frame_error_reg;
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always @(posedge clk) begin
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if (rst) begin
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m_axis_tdata_reg <= 0;
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m_axis_tvalid_reg <= 0;
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rxd_reg <= 1;
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prescale_reg <= 0;
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bit_cnt <= 0;
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busy_reg <= 0;
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overrun_error_reg <= 0;
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frame_error_reg <= 0;
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end else begin
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rxd_reg <= rxd;
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overrun_error_reg <= 0;
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frame_error_reg <= 0;
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if (m_axis_tvalid && m_axis_tready) begin
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m_axis_tvalid_reg <= 0;
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end
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if (prescale_reg > 0) begin
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prescale_reg <= prescale_reg - 1;
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end else if (bit_cnt > 0) begin
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if (bit_cnt > 8+1) begin
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if (!rxd_reg) begin
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bit_cnt <= bit_cnt - 1;
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prescale_reg <= (prescale << 3)-1;
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end else begin
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bit_cnt <= 0;
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prescale_reg <= 0;
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end
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end else if (bit_cnt > 1) begin
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bit_cnt <= bit_cnt - 1;
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prescale_reg <= (prescale << 3)-1;
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data_reg <= {rxd_reg, data_reg[8-1:1]};
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end else if (bit_cnt == 1) begin
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bit_cnt <= bit_cnt - 1;
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if (rxd_reg) begin
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m_axis_tdata_reg <= data_reg;
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m_axis_tvalid_reg <= 1;
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overrun_error_reg <= m_axis_tvalid_reg;
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end else begin
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frame_error_reg <= 1;
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end
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end
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end else begin
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busy_reg <= 0;
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if (!rxd_reg) begin
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prescale_reg <= (prescale << 2)-2;
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bit_cnt <= 8+2;
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data_reg <= 0;
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busy_reg <= 1;
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end
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end
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end
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end
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endmodule

‎flow/designs/src/uart-no-param/uart_tx.v‎

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/*
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Copyright (c) 2014-2017 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
8+
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9+
copies of the Software, and to permit persons to whom the Software is
10+
furnished to do so, subject to the following conditions:
11+
12+
The above copyright notice and this permission notice shall be included in
13+
all copies or substantial portions of the Software.
14+
15+
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16+
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17+
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18+
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19+
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream UART
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*/
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module uart_tx(
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input wire clk,
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input wire rst,
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/*
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* AXI input
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*/
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input wire [8-1:0] s_axis_tdata,
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input wire s_axis_tvalid,
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output wire s_axis_tready,
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/*
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* UART interface
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*/
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output wire txd,
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/*
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* Status
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*/
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output wire busy,
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/*
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* Configuration
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*/
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input wire [15:0] prescale
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);
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reg s_axis_tready_reg = 0;
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reg txd_reg = 1;
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reg busy_reg = 0;
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reg [8:0] data_reg = 0;
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reg [18:0] prescale_reg = 0;
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reg [3:0] bit_cnt = 0;
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assign s_axis_tready = s_axis_tready_reg;
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assign txd = txd_reg;
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assign busy = busy_reg;
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always @(posedge clk) begin
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if (rst) begin
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s_axis_tready_reg <= 0;
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txd_reg <= 1;
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prescale_reg <= 0;
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bit_cnt <= 0;
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busy_reg <= 0;
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end else begin
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if (prescale_reg > 0) begin
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s_axis_tready_reg <= 0;
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prescale_reg <= prescale_reg - 1;
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end else if (bit_cnt == 0) begin
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s_axis_tready_reg <= 1;
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busy_reg <= 0;
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if (s_axis_tvalid) begin
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s_axis_tready_reg <= !s_axis_tready_reg;
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prescale_reg <= (prescale << 3)-1;
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bit_cnt <= 8+1;
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data_reg <= {1'b1, s_axis_tdata};
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txd_reg <= 0;
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busy_reg <= 1;
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end
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end else begin
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if (bit_cnt > 1) begin
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bit_cnt <= bit_cnt - 1;
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prescale_reg <= (prescale << 3)-1;
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{data_reg, txd_reg} <= {1'b0, data_reg};
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end else if (bit_cnt == 1) begin
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bit_cnt <= bit_cnt - 1;
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prescale_reg <= (prescale << 3);
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txd_reg <= 1;
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end
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end
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end
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end
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endmodule

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