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malibertymaliberty
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Merge pull request #2998 from jeffng-or/cva6-frontend-mods
cva6 mods to support multiple SV front ends
2 parents 2eea2b1 + 186eed1 commit 9bc4c75

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5 files changed

+111
-65
lines changed

5 files changed

+111
-65
lines changed

‎flow/designs/asap7/cva6/config.mk‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -126,8 +126,8 @@ export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/cvfpu
126126
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/pmp/src/pmp.sv \
127127
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/pmp/src/pmp_entry.sv \
128128
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/pmp/src/pmp_data_if.sv \
129+
$(PLATFORM_DIR)/verilog/fakeram7_256x32.sv \
129130
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/common/local/util/tc_sram_wrapper.sv \
130-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/common/local/util/tc_sram_wrapper_cache_techno.sv \
131131
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv \
132132
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/common/local/util/sram.sv \
133133
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/common/local/util/sram_cache.sv \
@@ -181,6 +181,10 @@ export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include
181181

182182
VERILOG_DEFINES += -D HPDCACHE_ASSERT_OFF
183183

184+
export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram7_256x32.lef
185+
186+
export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/fakeram7_256x32.lib
187+
184188
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
185189

186190
export DIE_AREA = 0 0 200 200

‎flow/designs/src/cva6/common/local/util/sram_cache.sv‎

Lines changed: 56 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -52,25 +52,34 @@ module sram_cache #(
5252
rdata_o = rdata_user[DATA_AND_USER_WIDTH-1:DATA_WIDTH];
5353
ruser_o = rdata_user[USER_WIDTH-1:0];
5454
end
55-
tc_sram_wrapper_cache_techno #(
56-
.NumWords(NUM_WORDS), // Number of Words in data array
57-
.DataWidth(DATA_AND_USER_WIDTH),// Data signal width
58-
.ByteWidth(32'd8), // Width of a data byte
59-
.NumPorts(32'd1), // Number of read and write ports
60-
.Latency(32'd1), // Latency when the read data is available
61-
.SimInit(SIM_INIT), // Simulation initialization
62-
.BYTE_ACCESS(BYTE_ACCESS), // ACCESS byte or full word
63-
.PrintSimCfg(1'b0) // Print configuration
64-
) i_tc_sram_wrapper (
65-
.clk_i ( clk_i ),
66-
.rst_ni ( rst_ni ),
67-
.req_i ( req_i ),
68-
.we_i ( we_i ),
69-
.be_i ( be ),
70-
.wdata_i ( wdata_user ),
71-
.addr_i ( addr_i ),
72-
.rdata_o ( rdata_user )
73-
);
55+
fakeram7_256x32 i_tc_sram_wrapper(
56+
.clk ( clk_i ),
57+
.ce_in ( req_i ),
58+
.we_in ( we_i ),
59+
.wd_in ( wdata_user ),
60+
.addr_in ( addr_i ),
61+
.rd_out ( rdata_user )
62+
);
63+
64+
// tc_sram_wrapper_cache_techno #(
65+
// .NumWords(NUM_WORDS), // Number of Words in data array
66+
// .DataWidth(DATA_AND_USER_WIDTH),// Data signal width
67+
// .ByteWidth(32'd8), // Width of a data byte
68+
// .NumPorts(32'd1), // Number of read and write ports
69+
// .Latency(32'd1), // Latency when the read data is available
70+
// .SimInit(SIM_INIT), // Simulation initialization
71+
// .BYTE_ACCESS(BYTE_ACCESS), // ACCESS byte or full word
72+
// .PrintSimCfg(1'b0) // Print configuration
73+
// ) i_tc_sram_wrapper (
74+
// .clk_i ( clk_i ),
75+
// .rst_ni ( rst_ni ),
76+
// .req_i ( req_i ),
77+
// .we_i ( we_i ),
78+
// .be_i ( be ),
79+
// .wdata_i ( wdata_user ),
80+
// .addr_i ( addr_i ),
81+
// .rdata_o ( rdata_user )
82+
// );
7483
end else begin
7584
logic [DATA_WIDTH-1:0] wdata_user;
7685
logic [DATA_WIDTH-1:0] rdata_user;
@@ -82,25 +91,34 @@ module sram_cache #(
8291
rdata_o = rdata_user;
8392
ruser_o = '0;
8493
end
85-
tc_sram_wrapper_cache_techno #(
86-
.NumWords(NUM_WORDS), // Number of Words in data array
87-
.DataWidth(DATA_AND_USER_WIDTH),// Data signal width
88-
.ByteWidth(32'd8), // Width of a data byte
89-
.NumPorts(32'd1), // Number of read and write ports
90-
.Latency(32'd1), // Latency when the read data is available
91-
.SimInit(SIM_INIT), // Simulation initialization
92-
.BYTE_ACCESS(BYTE_ACCESS), // ACCESS byte or full word
93-
.PrintSimCfg(1'b0) // Print configuration
94-
) i_tc_sram_wrapper (
95-
.clk_i ( clk_i ),
96-
.rst_ni ( rst_ni ),
97-
.req_i ( req_i ),
98-
.we_i ( we_i ),
99-
.be_i ( be ),
100-
.wdata_i ( wdata_user ),
101-
.addr_i ( addr_i ),
102-
.rdata_o ( rdata_user )
103-
);
94+
fakeram7_256x32 i_tc_sram_wrapper(
95+
.clk ( clk_i ),
96+
.ce_in ( req_i ),
97+
.we_in ( we_i ),
98+
.wd_in ( wdata_user ),
99+
.addr_in ( addr_i ),
100+
.rd_out ( rdata_user )
101+
);
102+
103+
// tc_sram_wrapper_cache_techno #(
104+
// .NumWords(NUM_WORDS), // Number of Words in data array
105+
// .DataWidth(DATA_AND_USER_WIDTH),// Data signal width
106+
// .ByteWidth(32'd8), // Width of a data byte
107+
// .NumPorts(32'd1), // Number of read and write ports
108+
// .Latency(32'd1), // Latency when the read data is available
109+
// .SimInit(SIM_INIT), // Simulation initialization
110+
// .BYTE_ACCESS(BYTE_ACCESS), // ACCESS byte or full word
111+
// .PrintSimCfg(1'b0) // Print configuration
112+
// ) i_tc_sram_wrapper (
113+
// .clk_i ( clk_i ),
114+
// .rst_ni ( rst_ni ),
115+
// .req_i ( req_i ),
116+
// .we_i ( we_i ),
117+
// .be_i ( be ),
118+
// .wdata_i ( wdata_user ),
119+
// .addr_i ( addr_i ),
120+
// .rdata_o ( rdata_user )
121+
// );
104122
end
105123
end else begin
106124
sram #(

‎flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv‎

Lines changed: 20 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -39,18 +39,26 @@ module hpdcache_sram
3939
output logic [DATA_SIZE-1:0] rdata
4040
);
4141

42-
hpdcache_sram_1rw #(
43-
.ADDR_SIZE(ADDR_SIZE),
44-
.DATA_SIZE(DATA_SIZE),
45-
.DEPTH(DEPTH)
46-
) ram_i (
47-
.clk,
48-
.rst_n,
49-
.cs,
50-
.we,
51-
.addr,
52-
.wdata,
53-
.rdata
42+
fakeram7_256x32 ram_i (
43+
.clk(clk),
44+
.ce_in(cs),
45+
.we_in(we),
46+
.addr_in(addr),
47+
.wd_in(wdata),
48+
.rd_out(rdata)
5449
);
50+
// hpdcache_sram_1rw #(
51+
// .ADDR_SIZE(ADDR_SIZE),
52+
// .DATA_SIZE(DATA_SIZE),
53+
// .DEPTH(DEPTH)
54+
// ) ram_i (
55+
// .clk,
56+
// .rst_n,
57+
// .cs,
58+
// .we,
59+
// .addr,
60+
// .wdata,
61+
// .rdata
62+
// );
5563

5664
endmodule : hpdcache_sram

‎flow/designs/src/cva6/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv‎

Lines changed: 21 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -39,20 +39,27 @@ module hpdcache_sram_wbyteenable
3939
input logic [DATA_SIZE/8-1:0] wbyteenable,
4040
output logic [DATA_SIZE-1:0] rdata
4141
);
42-
43-
hpdcache_sram_wbyteenable_1rw #(
44-
.ADDR_SIZE(ADDR_SIZE),
45-
.DATA_SIZE(DATA_SIZE),
46-
.DEPTH(DEPTH)
47-
) ram_i (
48-
.clk,
49-
.rst_n,
50-
.cs,
51-
.we,
52-
.addr,
53-
.wdata,
54-
.wbyteenable,
55-
.rdata
42+
fakeram7_256x32 ram_i (
43+
.clk (clk),
44+
.ce_in(cs),
45+
.we_in(we),
46+
.addr_in(addr),
47+
.wd_in(wdata),
48+
.rd_out(rdata)
5649
);
50+
// hpdcache_sram_wbyteenable_1rw #(
51+
// .ADDR_SIZE(ADDR_SIZE),
52+
// .DATA_SIZE(DATA_SIZE),
53+
// .DEPTH(DEPTH)
54+
// ) ram_i (
55+
// .clk,
56+
// .rst_n,
57+
// .cs,
58+
// .we,
59+
// .addr,
60+
// .wdata,
61+
// .wbyteenable,
62+
// .rdata
63+
// );
5764

5865
endmodule : hpdcache_sram_wbyteenable

‎flow/platforms/asap7/verilog/fakeram7_256x32.sv‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
module fakeram7_256x32 (
2+
output reg [31:0] rd_out,
3+
input [7:0] addr_in,
4+
input we_in,
5+
input [31:0] wd_in,
6+
input clk,
7+
input ce_in
8+
);
9+
endmodule

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