Merge pull request #3329 from The-OpenROAD-Project-staging/secure-hier-flow-enh

made it easier to enable wrapped operator synthesis and operator mapping

Author: maliberty

docs/user/FlowVariables.md

@@ -219,6 +219,7 @@ configuration file.
 | <a name="SKIP_PIN_SWAP"></a>SKIP_PIN_SWAP| Do not use pin swapping as a transform to fix timing violations (default: use pin swapping).| |
 | <a name="SKIP_REPORT_METRICS"></a>SKIP_REPORT_METRICS| If set to 1, then metrics, report_metrics does nothing. Useful to speed up builds.| |
 | <a name="SLEW_MARGIN"></a>SLEW_MARGIN| Specifies a slew margin when fixing max slew violations. This option allows you to overfix.| |
+| <a name="SWAP_ARITH_OPERATORS"></a>SWAP_ARITH_OPERATORS| Improve timing QoR by swapping ALU and MULT arithmetic operators.| |
 | <a name="SYNTH_ARGS"></a>SYNTH_ARGS| Optional synthesis variables for yosys.| |
 | <a name="SYNTH_BLACKBOXES"></a>SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design.| |
 | <a name="SYNTH_GUT"></a>SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| |
@@ -255,6 +256,7 @@ configuration file.
 - [MIN_BUF_CELL_AND_PORTS](#MIN_BUF_CELL_AND_PORTS)
 - [SDC_FILE](#SDC_FILE)
 - [SDC_GUT](#SDC_GUT)
+- [SWAP_ARITH_OPERATORS](#SWAP_ARITH_OPERATORS)
 - [SYNTH_BLACKBOXES](#SYNTH_BLACKBOXES)
 - [SYNTH_GUT](#SYNTH_GUT)
 - [SYNTH_HDL_FRONTEND](#SYNTH_HDL_FRONTEND)
@@ -322,6 +324,7 @@ configuration file.
 - [SKIP_LAST_GASP](#SKIP_LAST_GASP)
 - [SKIP_PIN_SWAP](#SKIP_PIN_SWAP)
 - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
+- [SWAP_ARITH_OPERATORS](#SWAP_ARITH_OPERATORS)
 - [TAPCELL_TCL](#TAPCELL_TCL)
 - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
 - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)
@@ -346,6 +349,7 @@ configuration file.
 - [PLACE_PINS_ARGS](#PLACE_PINS_ARGS)
 - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT)
 - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
+- [SWAP_ARITH_OPERATORS](#SWAP_ARITH_OPERATORS)
 - [TIE_SEPARATION](#TIE_SEPARATION)
 
 ## cts variables

flow/scripts/floorplan.tcl

@@ -101,6 +101,11 @@ if { [env_var_exists_and_non_empty FOOTPRINT_TCL] } {
 # tie driving multiple buffers that drive multiple outputs.
 repair_tie_fanout_helper
 
+if { [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] } {
+  estimate_parasitics -placement
+  replace_arith_modules
+}
+
 if { [env_var_equals REMOVE_ABC_BUFFERS 1] } {
   # remove buffers inserted by yosys/abc
   remove_buffers

flow/scripts/load.tcl

@@ -18,9 +18,23 @@ proc load_design { design_file sdc_file } {
       }
     }
     read_verilog $::env(RESULTS_DIR)/$design_file
-    link_design $::env(DESIGN_NAME)
+    if {
+      [env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] ||
+      [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS]
+    } {
+      link_design -hier $::env(DESIGN_NAME)
+    } else {
+      link_design $::env(DESIGN_NAME)
+    }
   } elseif { $ext == ".odb" } {
-    read_db $::env(RESULTS_DIR)/$design_file
+    if {
+      [env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] ||
+      [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS]
+    } {
+      read_db -hier $::env(RESULTS_DIR)/$design_file
+    } else {
+      read_db $::env(RESULTS_DIR)/$design_file
+    }
   } else {
     error "Unrecognized input file $design_file"
   }

flow/scripts/resize.tcl

@@ -14,6 +14,10 @@ if { [env_var_exists_and_non_empty EARLY_SIZING_CAP_RATIO] } {
   log_cmd set_opt_config -set_early_sizing_cap_ratio $env(EARLY_SIZING_CAP_RATIO)
 }
 
+if { [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] } {
+  replace_arith_modules
+}
+
 repair_design_helper
 
 # hold violations are not repaired until after CTS

flow/scripts/synth.tcl

@@ -56,10 +56,13 @@ json -o $::env(RESULTS_DIR)/mem.json
 exec -- $::env(PYTHON_EXE) $::env(SCRIPTS_DIR)/mem_dump.py \
   --max-bits $::env(SYNTH_MEMORY_MAX_BITS) $::env(RESULTS_DIR)/mem.json
 
-if { ![env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] } {
-  synth -top $::env(DESIGN_NAME) -run fine: {*}$synth_full_args
-} else {
+if {
+  [env_var_exists_and_non_empty SYNTH_WRAPPED_OPERATORS] ||
+  [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS]
+} {
   source $::env(SCRIPTS_DIR)/synth_wrap_operators.tcl
+} else {
+  synth -top $::env(DESIGN_NAME) -run fine: {*}$synth_full_args
 }
 
 # Get rid of indigestibles

flow/scripts/synth_wrap_operators.tcl

@@ -10,8 +10,8 @@ set deferred_cells {
   {
     \$macc
     MACC_{CONFIG}_{Y_WIDTH}{%unused}
-    {BASE -map +/choices/han-carlson.v}
     {BOOTH -max_iter 1 -map ../flow/scripts/synth_wrap_operators-booth.v}
+    {BASE -map +/choices/han-carlson.v}
   }
 }
 

flow/scripts/variables.yaml

@@ -269,6 +269,13 @@ SYNTH_WRAPPED_OPERATORS:
     the flow.
   stages:
     - synth
+SWAP_ARITH_OPERATORS:
+  description: >
+    Improve timing QoR by swapping ALU and MULT arithmetic operators.
+  stages:
+    - synth
+    - floorplan
+    - place
 FLOORPLAN_DEF:
   description: |
     Use the DEF file to initialize floorplan.