synth: Add yosys-slang option; demonstrate on Ibex

Signed-off-by: Martin Povišer <[email protected]>

Author: povik

flow/designs/nangate45/ibex/config.mk

@@ -2,48 +2,32 @@ export DESIGN_NICKNAME = ibex
 export DESIGN_NAME = ibex_core
 export PLATFORM    = nangate45
 
-
-
-export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \
-                       $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v
-
-
-
+export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pkg.sv \
+    $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.sv \
+    $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.sv \
+    $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.sv \
+    $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.sv \
+    $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.sv \
+    $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.sv \
+    $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.sv \
+    $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.sv \
+    $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.sv \
+    $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.sv \
+    $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.sv \
+    $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.sv \
+    $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.sv \
+    $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.sv \
+    $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.sv \
+    $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.sv \
+    $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.sv \
+    $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.sv \
+    $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.sv \
+    $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/syn/rtl/prim_clock_gating.v
+
+export VERILOG_INCLUDE_DIRS = \
+    $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/lowrisc_ip/prim/rtl/
+
+export USE_YOSYS_SLANG = 1
 
 export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 

flow/designs/src/ibex/README.md

@@ -10,6 +10,6 @@ Cloned from https://github.com/lowRISC/ibex (`commit 77d801001554cce8fe69e742e96
 # Modifications
 
 - Default configuration from Repository.
-- Converted to verilog [using](https://github.com/zachjs/sv2v).
+- Pruned to only those source files which are used and moved most to the top directory. 
 - Added timing constraints.
 - Added LICENSE.