synth: Adjust verific port naming to match slang

Before

	module cva6
	input [0:0] clk_i
	input [0:0] rst_ni
	input [0:0] ipi_i
	input [0:0] time_irq_i
	input [0:0] debug_req_i
	output [0:0] rvfi_probes_o.csr.dcsr_q.ebreakvs
	output [0:0] rvfi_probes_o.csr.dcsr_q.ebreakvu
	output [0:0] rvfi_probes_o.csr.dcsr_q.ebreakm
	output [0:0] rvfi_probes_o.csr.dcsr_q.zero1
	output [0:0] rvfi_probes_o.csr.dcsr_q.ebreaks
	output [0:0] rvfi_probes_o.csr.dcsr_q.ebreaku
	output [0:0] rvfi_probes_o.csr.dcsr_q.stepie
	output [0:0] rvfi_probes_o.csr.dcsr_q.stopcount
	output [0:0] rvfi_probes_o.csr.dcsr_q.stoptime
	output [0:0] rvfi_probes_o.csr.dcsr_q.v
	output [0:0] rvfi_probes_o.csr.dcsr_q.mprven
	output [0:0] rvfi_probes_o.csr.dcsr_q.nmip
	output [0:0] rvfi_probes_o.csr.dcsr_q.step
	output [0:0] rvfi_probes_o.csr.fiom_q
	output [0:0] rvfi_probes_o.csr.pmpcfg_q[63].locked
	output [0:0] rvfi_probes_o.csr.pmpcfg_q[63].access_type.x
	output [0:0] rvfi_probes_o.csr.pmpcfg_q[63].access_type.w
	output [0:0] rvfi_probes_o.csr.pmpcfg_q[63].access_type.r
	output [0:0] rvfi_probes_o.csr.pmpcfg_q[62].locked
	output [0:0] rvfi_probes_o.csr.pmpcfg_q[62].access_type.x
	output [0:0] rvfi_probes_o.csr.pmpcfg_q[62].access_type.w
	output [0:0] rvfi_probes_o.csr.pmpcfg_q[62].access_type.r
	output [0:0] rvfi_probes_o.csr.pmpcfg_q[61].locked
	
	... and more

After

	module cva6
	input [0:0] clk_i
	input [0:0] rst_ni
	input [31:0] boot_addr_i
	input [31:0] hart_id_i
	input [1:0] irq_i
	input [0:0] ipi_i
	input [0:0] time_irq_i
	input [0:0] debug_req_i
	output [4294:0] rvfi_probes_o
	output [256:0] cvxif_req_o
	input [113:0] cvxif_resp_i
	output [373:0] noc_req_o
	input [145:0] noc_resp_i

Signed-off-by: Martin Povišer <[email protected]>

Author: povik

flow/scripts/synth_preamble.tcl

@@ -59,6 +59,7 @@ proc read_design_sources { } {
       verific -vlog-define {*}$::env(VERILOG_DEFINES)
     }
     verific -sv2012 {*}$::env(VERILOG_FILES)
+    verific -import -no-split-complex-ports $::env(DESIGN_NAME)
   } elseif { ![env_var_exists_and_non_empty SYNTH_HDL_FRONTEND] } {
     verilog_defaults -push
     if { [env_var_exists_and_non_empty VERILOG_DEFINES] } {