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asap7, ihp-sg13g2: Insert fresh RC fit
Log from asap7 fit: $ util/correlateRC.py -cap_unit ff results/asap7/*/base/6_net_rc.csv reading results/asap7/aes/base/6_net_rc.csv reading results/asap7/cva6/base/6_net_rc.csv reading results/asap7/ibex/base/6_net_rc.csv reading results/asap7/riscv32i/base/6_net_rc.csv # Resistance coefficient of determination: 0.9736 # Capacitance coefficient of determination: 0.9632 # Updated layer resistance kohm/um capacitance ff/um set_layer_rc -layer M1 -resistance 7.04175E-02 -capacitance -4.85208E-02 set_layer_rc -layer M2 -resistance 4.62311E-02 -capacitance 1.84542E-01 set_layer_rc -layer M3 -resistance 3.63251E-02 -capacitance 1.53955E-01 set_layer_rc -layer M4 -resistance 2.03083E-02 -capacitance 1.89434E-01 set_layer_rc -layer M5 -resistance 1.93005E-02 -capacitance 1.71593E-01 set_layer_rc -layer M6 -resistance 1.18619E-02 -capacitance 1.76146E-01 set_layer_rc -layer M7 -resistance 1.25311E-02 -capacitance 1.47030E-01 # Combined fit: set_wire_rc -resistance 3.26320E-02 -capacitance 1.72845E-01 # Split signal/clock fit: set_wire_rc -signal -resistance 3.23151E-02 -capacitance 1.73323E-01 set_wire_rc -clock -resistance 5.13971E-02 -capacitance 1.44549E-01 Log from ihp-sg13g2 fit: $ util/correlateRC.py results/ihp-sg13g2/*/base/6_net_rc.csv reading results/ihp-sg13g2/aes/base/6_net_rc.csv reading results/ihp-sg13g2/gcd/base/6_net_rc.csv reading results/ihp-sg13g2/ibex/base/6_net_rc.csv reading results/ihp-sg13g2/riscv32i/base/6_net_rc.csv reading results/ihp-sg13g2/spi/base/6_net_rc.csv # Resistance coefficient of determination: 0.7364 # Capacitance coefficient of determination: 0.9689 # Updated layer resistance kohm/um capacitance pf/um set_layer_rc -layer Metal1 -resistance 8.54576E-03 -capacitance -1.05290E-05 set_layer_rc -layer Metal2 -resistance 2.53519E-03 -capacitance 1.69121E-04 set_layer_rc -layer Metal3 -resistance 1.54329E-03 -capacitance 1.82832E-04 set_layer_rc -layer Metal4 -resistance 6.31424E-04 -capacitance 1.66454E-04 set_layer_rc -layer Metal5 -resistance 6.84051E-04 -capacitance 8.57431E-05 # Combined fit: set_wire_rc -resistance 2.08008E-03 -capacitance 1.72560E-04 # Split signal/clock fit: set_wire_rc -signal -resistance 2.07259E-03 -capacitance 1.73072E-04 set_wire_rc -clock -resistance 2.48603E-03 -capacitance 1.44812E-04 Signed-off-by: Martin Povišer <[email protected]>
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flow/platforms/asap7/setRC.tcl

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# Liberty units are fF,kOhm
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set_layer_rc -layer M1 -capacitance 1.1368e-01 -resistance 1.3889e-01
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set_layer_rc -layer M2 -capacitance 1.3426e-01 -resistance 2.4222e-02
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set_layer_rc -layer M3 -capacitance 1.2918e-01 -resistance 2.4222e-02
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set_layer_rc -layer M4 -capacitance 1.1396e-01 -resistance 1.6778e-02
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set_layer_rc -layer M5 -capacitance 1.3323e-01 -resistance 1.4677e-02
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set_layer_rc -layer M6 -capacitance 1.1575e-01 -resistance 1.0371e-02
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set_layer_rc -layer M7 -capacitance 1.3293e-01 -resistance 9.6720e-03
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set_layer_rc -layer M8 -capacitance 1.1822e-01 -resistance 7.4310e-03
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set_layer_rc -layer M9 -capacitance 1.3497e-01 -resistance 6.8740e-03
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# correlation result (aes, cva6, ibex, riscv32i)
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# M1 capacitance fixed up from -4.8e-02 to 1e-10 as a minuscule positive value
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set_layer_rc -layer M1 -resistance 7.04175E-02 -capacitance 1e-10
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set_layer_rc -layer M2 -resistance 4.62311E-02 -capacitance 1.84542E-01
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set_layer_rc -layer M3 -resistance 3.63251E-02 -capacitance 1.53955E-01
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set_layer_rc -layer M4 -resistance 2.03083E-02 -capacitance 1.89434E-01
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set_layer_rc -layer M5 -resistance 1.93005E-02 -capacitance 1.71593E-01
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set_layer_rc -layer M6 -resistance 1.18619E-02 -capacitance 1.76146E-01
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set_layer_rc -layer M7 -resistance 1.25311E-02 -capacitance 1.47030E-01
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set_wire_rc -signal -resistance 3.23151E-02 -capacitance 1.73323E-01
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set_wire_rc -clock -resistance 5.13971E-02 -capacitance 1.44549E-01
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set_layer_rc -via V1 -resistance 1.72E-02
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set_layer_rc -via V2 -resistance 1.72E-02
@@ -17,5 +18,3 @@ set_layer_rc -via V5 -resistance 1.18E-02
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set_layer_rc -via V6 -resistance 8.20E-03
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set_layer_rc -via V7 -resistance 8.20E-03
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set_layer_rc -via V8 -resistance 6.30E-03
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set_wire_rc -layer M3
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# correlateRC.py gcd,ibex,aes,jpeg,chameleon,riscv32i,chameleon_hier
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# cap units pf/um
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set_layer_rc -layer Metal1 -capacitance 3.49E-05 -resistance 0.135e-03
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set_layer_rc -layer Metal2 -capacitance 1.81E-05 -resistance 0.103e-03
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set_layer_rc -layer Metal3 -capacitance 2.14962E-04 -resistance 0.103e-03
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set_layer_rc -layer Metal4 -capacitance 1.48128E-04 -resistance 0.103e-03
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set_layer_rc -layer Metal5 -capacitance 1.54087E-04 -resistance 0.103e-03
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set_layer_rc -layer TopMetal1 -capacitance 1.54087E-04 -resistance 0.021e-03
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set_layer_rc -layer TopMetal2 -capacitance 1.54087E-04 -resistance 0.0145e-03
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# end correlate
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# correlation result (aes, gcd, ibex, riscv32i, spi)
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# Metal1 capacitance fixed up from -1.1e-05 to 1e-10 as a minuscule positive value
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set_layer_rc -layer Metal1 -resistance 8.54576E-03 -capacitance 1e-10
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set_layer_rc -layer Metal2 -resistance 2.53519E-03 -capacitance 1.69121E-04
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set_layer_rc -layer Metal3 -resistance 1.54329E-03 -capacitance 1.82832E-04
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set_layer_rc -layer Metal4 -resistance 6.31424E-04 -capacitance 1.66454E-04
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set_layer_rc -layer Metal5 -resistance 6.84051E-04 -capacitance 8.57431E-05
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set_wire_rc -signal -resistance 2.07259E-03 -capacitance 1.73072E-04
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set_wire_rc -clock -resistance 2.48603E-03 -capacitance 1.44812E-04
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set_layer_rc -via Via1 -resistance 2.0E-3
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set_layer_rc -via Via2 -resistance 2.0E-3
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set_layer_rc -via Via3 -resistance 2.0E-3
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set_layer_rc -via Via4 -resistance 2.0E-3
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set_layer_rc -via TopVia1 -resistance 0.4E-3
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set_layer_rc -via TopVia2 -resistance 0.22E-3
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set_wire_rc -signal -layer Metal2
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set_wire_rc -clock -layer Metal5

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