Increased rapidus cva6 util to 45 for Verific

tcllint fixes

Signed-off-by: Jeff Ng <[email protected]>

Author: jeffng-or

flow/designs/rapidus2hp/cva6/config.mk

@@ -98,11 +98,11 @@ export SYNTH_HIERARCHICAL = 1
 ifeq ($(SYNTH_HDL_FRONTEND),verific)
   # Reduce utilization for verific since it runs into issues with DPL not being
   # able to place instances or with one-site gap/overlap issues
-  export CORE_UTILIZATION       = 35
+  export CORE_UTILIZATION       = 45
 else
   # Reduce the amount of resizing done between GPL and DPL
   export EARLY_SIZING_CAP_RATIO = 6
-  export CORE_UTILIZATION       = 45
+  export CORE_UTILIZATION       = 50
 endif
 
 export CORE_MARGIN            = 2
@@ -118,3 +118,5 @@ export SKIP_LAST_GASP ?= 1
 
 # For use with SYNTH_HIERARCHICAL
 export SYNTH_MINIMUM_KEEP_SIZE ?= 40000
+
+#export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/io_constraints.tcl

flow/designs/rapidus2hp/cva6/io_constraints.tcl

@@ -1,15 +1,15 @@
 # left (bottom to top)
 # cvxif_req_o
-# axi_req_o - noc_req_o in ours
-# scan_output - doesn't exist in ours
-set_io_pin_constraint -group -order -region left:20-38.7 -pin_names {cvxif_req_o*}
-set_io_pin_constraint -group -order -region left:38.8-90.2 -pin_names {noc_req_o*}
+# axi_req_o - renamed to noc_req_o in 716d21c
+# scan_output - inserted by commercial tool?
+set_io_pin_constraint -group -order -region left:4.09-40.70 -pin_names {cvxif_req_o[*]}
+set_io_pin_constraint -group -order -region left:40.85-90.13 -pin_names {noc_req_o[*]}
 
 # right (bottom to top)
-# scan_input - doesn't exist in ours
-# test_mode - doesn't exist in ours
-# scan_enable - doesn't exist in ours
-# axi_resp_i - noc_resp_i in ours
+# scan_input - inserted by commercial tool?
+# test_mode - inserted by commercial tool?
+# scan_enable - inserted by commercial tool?
+# axi_resp_i - renamed to noc_resp_i in 716d21c
 # cvxif_resp_i
 # debug_req_i
 # time_irq_i
@@ -19,16 +19,20 @@ set_io_pin_constraint -group -order -region left:38.8-90.2 -pin_names {noc_req_o
 # boot_addr_i
 # rst_ni
 # clk_i
-set_io_pin_constraint -group -order -region right:5-31.4 -pin_names {noc_resp_i*}
-set_io_pin_constraint -group -order -region right:31.5-73.1 -pin_names {cvxif_resp_i*}
-set_io_pin_constraint -group -order -region right:73.3-73.7 -pin_names {debug_req_i \
-								        time_irq_i ipi_i}
-set_io_pin_constraint -group -order -region right:74-74.3 -pin_names {irq_i*}
-set_io_pin_constraint -group -order -region right:74.5-82 -pin_names {hart_id_i*}
-set_io_pin_constraint -group -order -region right:82.2-89.8 -pin_names {boot_addr_i*}
-set_io_pin_constraint -group -order -region right:89.9-90.3 -pin_names {rst_n_i clk_i}
+# Not enough space for the amount of pins, so upper bound increased from 25.34 to 45.34 - ripples
+# through rest of pins
+set_io_pin_constraint -group -order -region right:5.25-45.34 -pin_names {noc_resp_i[*]}
+set_io_pin_constraint -group -order -region right:45.62-93.07 -pin_names {cvxif_resp_i[*]}
+set_io_pin_constraint -group -order -region right:93.32-93.73 \
+  -pin_names {
+    debug_req_i time_irq_i ipi_i
+  }
+set_io_pin_constraint -group -order -region right:94.01-94.28 -pin_names {irq_i[*]}
+set_io_pin_constraint -group -order -region right:94.51-102.01 -pin_names {hart_id_i[*]}
+set_io_pin_constraint -group -order -region right:102.25-109.74 -pin_names {boot_addr_i[*]}
+set_io_pin_constraint -group -order -region right:109.99-110.25 -pin_names {rst_ni clk_i}
 
-# don't exist in reference design implementation - does it make us I/O bound?
+# The rvfi_probes_o pins don't exist in reference design implementation
 # put a third of them on the top, a third on the bottom, and let the placer
 # decide where to put the remaining third
 set num_rvfi_probes_ports 4295
@@ -42,5 +46,6 @@ for { } { $i < $third_rvfi_probes_ports * 2 } { incr i } {
   lappend bottom_group "rvfi_probes_o\[$i\]"
 }
 
+
 set_io_pin_constraint -group -order -region bottom:* -pin_names $top_group
 set_io_pin_constraint -group -order -region top:* -pin_names $bottom_group