Merge remote-tracking branch 'origin/master' into secure-gpl-modify-td-max-weight

Author: gudeh

docs/user/FlowVariables.md

@@ -94,6 +94,7 @@ configuration file.
 | <a name="FILL_CELLS"></a>FILL_CELLS| Fill cells are used to fill empty sites. If not set or empty, fill cell insertion is skipped.| | |
 | <a name="FILL_CONFIG"></a>FILL_CONFIG| JSON rule file for metal fill during chip finishing.| | |
 | <a name="FLOORPLAN_DEF"></a>FLOORPLAN_DEF| Use the DEF file to initialize floorplan.| | |
+| <a name="FLOW_VARIANT"></a>FLOW_VARIANT| Flow variant to use, used in the flow variant directory name.| base| |
 | <a name="GDS_ALLOW_EMPTY"></a>GDS_ALLOW_EMPTY| Regular expression of module names of macros that have no .gds file| | |
 | <a name="GDS_FILES"></a>GDS_FILES| Path to platform GDS files.| | |
 | <a name="GENERATE_ARTIFACTS_ON_FAILURE"></a>GENERATE_ARTIFACTS_ON_FAILURE| For instance Bazel needs artifacts (.odb and .rpt files) on a failure to allow the user to save hours on re-running the failed step locally, but when working with a Makefile flow, it is more natural to fail the step and leave the user to manually inspect the logs and artifacts directly via the file system. Set to 1 to change the behavior to generate artifacts upon failure to e.g. do a global route. The exit code will still be non-zero on all other failures that aren't covered by the "useful to inspect the artifacts on failure" use-case. Example: just like detailed routing, a global route that fails with congestion, is not a build failure(as in exit code non-zero), it is a successful(as in zero exit code) global route that produce reports detailing the problem. Detailed route will not proceed, if there is global routing congestion This allows build systems, such as bazel, to create artifacts for global and detailed route, even if the operation had problems, without having know about the semantics between global and detailed route. Considering that global and detailed route can run for a long time and use a lot of memory, this allows inspecting results on a laptop for a build that ran on a server.| 0| |
@@ -182,7 +183,7 @@ configuration file.
 | <a name="SYNTH_HIERARCHICAL"></a>SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0| |
 | <a name="SYNTH_KEEP_MODULES"></a>SYNTH_KEEP_MODULES| Mark modules to keep from getting removed in flattening.| | |
 | <a name="SYNTH_MEMORY_MAX_BITS"></a>SYNTH_MEMORY_MAX_BITS| Maximum number of bits for memory synthesis.| 4096| |
-| <a name="SYNTH_MINIMUM_KEEP_SIZE"></a>SYNTH_MINIMUM_KEEP_SIZE| For hierarchical synthesis, we keep modules of larger area than given by this variable and flatten smaller modules. The area unit used is the size of a basic nand2 gate from the platform's standard cell library. The default value is platform specific.| | |
+| <a name="SYNTH_MINIMUM_KEEP_SIZE"></a>SYNTH_MINIMUM_KEEP_SIZE| For hierarchical synthesis, we keep modules of larger area than given by this variable and flatten smaller modules. The area unit used is the size of a basic nand2 gate from the platform's standard cell library. The default value is platform specific.| 0| |
 | <a name="SYNTH_NETLIST_FILES"></a>SYNTH_NETLIST_FILES| Skips synthesis and uses the supplied netlist files. If the netlist files contains duplicate modules, which can happen when using hierarchical synthesis on indvidual netlist files and combining here, subsequent modules are silently ignored and only the first module is used.| | |
 | <a name="SYNTH_WRAPPED_OPERATORS"></a>SYNTH_WRAPPED_OPERATORS| Synthesize multiple architectural options for each arithmetic operator in the design. These options are available for switching among in later stages of the flow.| | |
 | <a name="TAPCELL_TCL"></a>TAPCELL_TCL| Path to Endcap and Welltie cells file.| | |
@@ -392,6 +393,7 @@ configuration file.
 - [ENABLE_DPO](#ENABLE_DPO)
 - [FASTROUTE_TCL](#FASTROUTE_TCL)
 - [FILL_CONFIG](#FILL_CONFIG)
+- [FLOW_VARIANT](#FLOW_VARIANT)
 - [GDS_FILES](#GDS_FILES)
 - [GENERATE_ARTIFACTS_ON_FAILURE](#GENERATE_ARTIFACTS_ON_FAILURE)
 - [GLOBAL_PLACEMENT_ARGS](#GLOBAL_PLACEMENT_ARGS)

flow/MODULE.bazel.lock

@@ -1,7 +1,3 @@
-# settings.mk is not under source control. Put variables into this
-# file to avoid having to adding the to the make command line.
--include settings.mk
-
 # ==============================================================================
 # Uncomment or add the design to run
 # ==============================================================================
@@ -159,15 +155,10 @@ include $(PLATFORM_DIR)/config.mk
 # is no way to escape space in defaults.py and get "foreach" to work.
 $(foreach line,$(shell $(SCRIPTS_DIR)/defaults.py),$(eval export $(subst __SPACE__, ,$(line))))
 
-# If the design, nor $(PLATFORM_DIR)/config.mk provided a default, provide one here
-export SYNTH_MINIMUM_KEEP_SIZE ?= 0
-
 # Not normally adjusted by user
 export SYNTH_OPERATIONS_ARGS ?= -extra-map $(FLOW_HOME)/platforms/common/lcu_kogge_stone.v
 export SYNTH_FULL_ARGS ?= $(SYNTH_ARGS) $(SYNTH_OPERATIONS_ARGS)
 
-export FLOW_VARIANT ?= base
-
 # Setup working directories
 export DESIGN_NICKNAME ?= $(DESIGN_NAME)
 

flow/Makefile

@@ -2,7 +2,7 @@ current_design jpeg_encoder
 
 set clk_name  clk 
 set clk_port_name clk
-set clk_period 1100 
+set clk_period 900
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]

flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc

@@ -48,7 +48,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": 0.0,
+        "value": -71.1,
         "compare": ">="
     },
     "finish__design__instance__area": {

flow/designs/asap7/jpeg/rules-base.json

@@ -1,6 +1,6 @@
 set clk_name  clk
 set clk_port_name clk
-set clk_period 6 
+set clk_period 6
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]

flow/designs/gf180/uart-blocks/constraint.sdc

@@ -2,7 +2,7 @@ current_design ibex_core
 
 set clk_name  core_clock
 set clk_port_name clk_i
-set clk_period 10.75
+set clk_period 10.0
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]

flow/designs/ihp-sg13g2/ibex/constraint.sdc

@@ -48,7 +48,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -0.43,
+        "value": -1.03,
         "compare": ">="
     },
     "finish__design__instance__area": {

flow/designs/ihp-sg13g2/ibex/rules-base.json

@@ -1,6 +1,6 @@
 set clk_name  clk
 set clk_port_name clk
-set clk_period 10.0 
+set clk_period 6.0
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]

flow/designs/ihp-sg13g2/riscv32i/constraint.sdc

@@ -28,43 +28,43 @@
         "compare": "<="
     },
     "globalroute__antenna_diodes_count": {
-        "value": 322,
+        "value": 310,
         "compare": "<="
     },
     "detailedroute__route__wirelength": {
-        "value": 771955,
+        "value": 771195,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
         "value": 0,
         "compare": "<="
     },
     "detailedroute__antenna__violating__nets": {
-        "value": 16,
+        "value": 14,
         "compare": "<="
     },
     "detailedroute__antenna_diodes_count": {
         "value": 5,
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": 0.0,
+        "value": -0.98,
         "compare": ">="
     },
     "finish__design__instance__area": {
         "value": 411968,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {
-        "value": 10,
+        "value": 523,
         "compare": "<="
     },
     "finish__timing__drv__hold_violation_count": {
         "value": 10,
         "compare": "<="
     },
     "finish__timing__wns_percent_delay": {
-        "value": -10.0,
+        "value": -24.94,
         "compare": ">="
     }
 }