mock-cpu: remove set_input/output_delays

Not idiomatic for the use-case where the mock-cpu
would be connected into an SoC where timing closure
is checked.

setting set_input_delay in particular is problematic
because it can lead to hold cells which should not be
used at all, or if they have to be used, they should
be inserted where the mock-cpu is used at the SoC level,
not inside the mock-cpu macro.

set_input/output_delay would be more approperiate at
the top level of an SoC on the pins connecting to
the outside world.

Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

flow/designs/asap7/mock-cpu/constraint.sdc

@@ -21,15 +21,30 @@ set_clock_groups -group $clk1_name -group $clk2_name -asynchronous -allow_paths
 set_false_path -from [get_ports *rst_n]
 set_false_path -to [get_ports *rst_n]
 
-# Give the world outside of the FIFO time to operate
-# on the cycle it is reading/writiing to the FIFO
-set min_percent 0.1
-set max_percent 0.5
-
-set_input_delay -clock $clk2_name -max [expr $clk2_period * $max_percent] [match_pins .* input 0]
-set_output_delay -clock $clk2_name -max [expr $clk2_period * $max_percent] [match_pins .* output 0]
-set_input_delay -clock $clk2_name -min [expr $clk2_period * $min_percent] [match_pins .* input 0]
-set_output_delay -clock $clk2_name -min [expr $clk2_period * $min_percent] [match_pins .* output 0]
+# The mock-cpu is a macro connecting to a slower peripheral bus and possibly DRAM.
+# Avoid using set_input/output_delay here.
+# Register-to-register paths are checked at the mock-cpu level or from the mock-cpu
+# .lib file to an external register.
+# Timing closure is ensured at the SoC level where the mock-cpu is connected.
+# Instead, set strict optimization targets for inputs and outputs to ensure
+# constraints are not too loose.
+set non_clk_inputs {}
+set clock_ports [list [get_ports $clk1_name] [get_ports $clk2_name]]
+foreach input [all_inputs] {
+  if {[lsearch -exact $clock_ports $input] == -1} {
+    lappend non_clk_inputs $input
+  }
+}
+
+set_max_delay 80 -from $non_clk_inputs -to [all_outputs]
+group_path -name in2out -from $non_clk_inputs -to [all_outputs]
+
+set all_register_outputs [get_pins -of_objects [all_registers] -filter {direction == output}]
+set_max_delay 80 -from $non_clk_inputs -to [all_registers]
+set_max_delay 80 -from $all_register_outputs -to [all_outputs]
+group_path -name in2reg -from $non_clk_inputs -to [all_registers]
+group_path -name reg2out -from [all_registers] -to [all_outputs]
+group_path -name reg2reg -from [all_registers] -to [all_registers]
 
 ## Dual clock fifo timing constraints
 # Using fastest clock as constaint