variables.yaml: review feedback

Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

docs/user/FlowVariables.md

@@ -160,31 +160,31 @@ configuration file.
 | VERILOG_FILES | The path to the design Verilog files or JSON files providing a description of modules (check `yosys -h write_json` for more details). |
 | VERILOG_INCLUDE_DIRS | Specifies the include directories for the Verilog input files. |
 | VERILOG_TOP_PARAMS | Apply toplevel params (if exist). |
-## synth
+## synth variables
 
-ABC_AREA ABC_CLOCK_PERIOD_IN_PS ABC_DRIVER_CELL ABC_LOAD_IN_FF ADDER_MAP_FILE ADDITIONAL_FILES ADDITIONAL_GDS ADDITIONAL_LEFS ADDITIONAL_LIBS BLOCKS CAP_MARGIN CDL_FILES CLKGATE_MAP_FILE CORNER DESIGN_NAME DESIGN_NICKNAME DFF_LIB_FILES DONT_USE_CELLS DONT_USE_LIBS DPO_MAX_DISPLACEMENT ENABLE_DPO FASTROUTE_TCL FILL_CELLS FILL_CONFIG GDS_FILES GENERATE_ARTIFACTS_ON_FAILURE GLOBAL_PLACEMENT_ARGS GND_NETS_VOLTAGES GUI_NO_TIMING IR_DROP_LAYER KLAYOUT_TECH_FILE LATCH_MAP_FILE LIB_FILES MACRO_EXTENSION MAX_UNGROUP_SIZE MIN_BUF_CELL_AND_PORTS PLACE_DENSITY_LB_ADDON PLATFORM PRESERVE_CELLS PROCESS PWR_NETS_VOLTAGES RCX_RULES RECOVER_POWER REPAIR_PDN_VIA_LAYER RESYNTH_AREA_RECOVER RESYNTH_TIMING_RECOVER SC_LEF SDC_FILE SEAL_GDS SET_RC_TCL SKIP_INCREMENTAL_REPAIR SKIP_REPORT_METRICS SLEW_MARGIN SYNTH_ARGS SYNTH_HIERARCHICAL TAP_CELL_NAME TECH_LEF TIEHI_CELL_AND_PORT TIELO_CELL_AND_PORT USE_FILL VERILOG_FILES VERILOG_INCLUDE_DIRS VERILOG_TOP_PARAMS
+ABC_AREA ABC_CLOCK_PERIOD_IN_PS ABC_DRIVER_CELL ABC_LOAD_IN_FF ADDER_MAP_FILE CLKGATE_MAP_FILE LATCH_MAP_FILE MAX_UNGROUP_SIZE MIN_BUF_CELL_AND_PORTS RESYNTH_AREA_RECOVER RESYNTH_TIMING_RECOVER SYNTH_HIERARCHICAL TIEHI_CELL_AND_PORT TIELO_CELL_AND_PORT VERILOG_FILES VERILOG_INCLUDE_DIRS VERILOG_TOP_PARAMS
 
-## floorplan
+## floorplan variables
 
-ADDITIONAL_FILES ADDITIONAL_GDS ADDITIONAL_LEFS ADDITIONAL_LIBS BLOCKS CAP_MARGIN CDL_FILES CORE_AREA CORE_ASPECT_RATIO CORE_MARGIN CORE_UTILIZATION CORNER DESIGN_NAME DESIGN_NICKNAME DFF_LIB_FILES DIE_AREA DONT_USE_CELLS DONT_USE_LIBS DPO_MAX_DISPLACEMENT ENABLE_DPO FASTROUTE_TCL FILL_CELLS FILL_CONFIG FLOORPLAN_DEF GDS_FILES GENERATE_ARTIFACTS_ON_FAILURE GLOBAL_PLACEMENT_ARGS GND_NETS_VOLTAGES GUI_NO_TIMING IO_PLACER_H IO_PLACER_V IR_DROP_LAYER KLAYOUT_TECH_FILE LIB_FILES MACRO_BLOCKAGE_HALO MACRO_EXTENSION MACRO_HALO_X MACRO_HALO_Y MACRO_PLACEMENT MACRO_PLACEMENT_TCL MACRO_PLACE_CHANNEL MACRO_PLACE_HALO MACRO_WRAPPERS MAKE_TRACKS PDN_TCL PLACE_DENSITY PLACE_DENSITY_LB_ADDON PLACE_SITE PLATFORM PRESERVE_CELLS PROCESS PWR_NETS_VOLTAGES RCX_RULES RECOVER_POWER REPAIR_PDN_VIA_LAYER RTLMP_FLOW SC_LEF SDC_FILE SEAL_GDS SET_RC_TCL SKIP_INCREMENTAL_REPAIR SKIP_REPORT_METRICS SLEW_MARGIN SYNTH_ARGS TAPCELL_TCL TAP_CELL_NAME TECH_LEF TNS_END_PERCENT USE_FILL
+CELL_PAD_IN_SITES_GLOBAL_PLACEMENT CORE_AREA CORE_ASPECT_RATIO CORE_MARGIN CORE_UTILIZATION DIE_AREA FLOORPLAN_DEF IO_PLACER_H IO_PLACER_V MACRO_BLOCKAGE_HALO MACRO_HALO_X MACRO_HALO_Y MACRO_PLACEMENT MACRO_PLACEMENT_TCL MACRO_PLACE_CHANNEL MACRO_PLACE_HALO MACRO_WRAPPERS MAKE_TRACKS PDN_TCL PLACE_DENSITY PLACE_SITE RTLMP_FLOW TAPCELL_TCL TNS_END_PERCENT
 
-## place
+## place variables
 
-ADDITIONAL_FILES ADDITIONAL_GDS ADDITIONAL_LEFS ADDITIONAL_LIBS BLOCKS CAP_MARGIN CDL_FILES CELL_PAD_IN_SITES_DETAIL_PLACEMENT CELL_PAD_IN_SITES_GLOBAL_PLACEMENT CORNER DESIGN_NAME DESIGN_NICKNAME DFF_LIB_FILES DONT_USE_CELLS DONT_USE_LIBS DPO_MAX_DISPLACEMENT ENABLE_DPO FASTROUTE_TCL FILL_CELLS FILL_CONFIG GDS_FILES GENERATE_ARTIFACTS_ON_FAILURE GLOBAL_PLACEMENT_ARGS GND_NETS_VOLTAGES GPL_ROUTABILITY_DRIVEN GPL_TIMING_DRIVEN GUI_NO_TIMING IO_PLACER_H IO_PLACER_V IR_DROP_LAYER KLAYOUT_TECH_FILE LIB_FILES MACRO_EXTENSION MAX_ROUTING_LAYER MIN_ROUTING_LAYER PLACE_DENSITY PLACE_DENSITY_LB_ADDON PLATFORM PRESERVE_CELLS PROCESS PWR_NETS_VOLTAGES RCX_RULES RECOVER_POWER REPAIR_PDN_VIA_LAYER ROUTING_LAYER_ADJUSTMENT SC_LEF SDC_FILE SEAL_GDS SET_RC_TCL SKIP_INCREMENTAL_REPAIR SKIP_REPORT_METRICS SLEW_MARGIN SYNTH_ARGS TAP_CELL_NAME TECH_LEF USE_FILL
+CELL_PAD_IN_SITES_DETAIL_PLACEMENT CELL_PAD_IN_SITES_GLOBAL_PLACEMENT GPL_ROUTABILITY_DRIVEN GPL_TIMING_DRIVEN IO_PLACER_H IO_PLACER_V MAX_ROUTING_LAYER MIN_ROUTING_LAYER PLACE_DENSITY ROUTING_LAYER_ADJUSTMENT TIEHI_CELL_AND_PORT TIELO_CELL_AND_PORT
 
-## cts
+## cts variables
 
-ADDITIONAL_FILES ADDITIONAL_GDS ADDITIONAL_LEFS ADDITIONAL_LIBS BLOCKS CAP_MARGIN CDL_FILES CORNER CTS_ARGS CTS_BUF_DISTANCE CTS_CLUSTER_DIAMETER CTS_CLUSTER_SIZE CTS_SNAPSHOT DESIGN_NAME DESIGN_NICKNAME DETAILED_METRICS DFF_LIB_FILES DONT_USE_CELLS DONT_USE_LIBS DPO_MAX_DISPLACEMENT ENABLE_DPO EQUIVALENCE_CHECK FASTROUTE_TCL FILL_CELLS FILL_CONFIG GDS_FILES GENERATE_ARTIFACTS_ON_FAILURE GLOBAL_PLACEMENT_ARGS GND_NETS_VOLTAGES GUI_NO_TIMING HOLD_SLACK_MARGIN IR_DROP_LAYER KLAYOUT_TECH_FILE LIB_FILES MACRO_EXTENSION PLACE_DENSITY_LB_ADDON PLATFORM POST_CTS_TCL PRESERVE_CELLS PROCESS PWR_NETS_VOLTAGES RCX_RULES RECOVER_POWER REMOVE_CELLS_FOR_EQY REPAIR_PDN_VIA_LAYER SC_LEF SDC_FILE SEAL_GDS SETUP_SLACK_MARGIN SET_RC_TCL SKIP_CTS_REPAIR_TIMING SKIP_GATE_CLONING SKIP_INCREMENTAL_REPAIR SKIP_PIN_SWAP SKIP_REPORT_METRICS SLEW_MARGIN SYNTH_ARGS TAP_CELL_NAME TECH_LEF TNS_END_PERCENT USE_FILL
+CELL_PAD_IN_SITES_DETAIL_PLACEMENT CTS_ARGS CTS_BUF_DISTANCE CTS_CLUSTER_DIAMETER CTS_CLUSTER_SIZE CTS_SNAPSHOT DETAILED_METRICS EQUIVALENCE_CHECK POST_CTS_TCL REMOVE_CELLS_FOR_EQY SKIP_CTS_REPAIR_TIMING TNS_END_PERCENT
 
-## grt
+## grt variables
 
-ADDITIONAL_FILES ADDITIONAL_GDS ADDITIONAL_LEFS ADDITIONAL_LIBS BLOCKS CAP_MARGIN CDL_FILES CORNER DESIGN_NAME DESIGN_NICKNAME DETAILED_METRICS DFF_LIB_FILES DONT_USE_CELLS DONT_USE_LIBS DPO_MAX_DISPLACEMENT ENABLE_DPO FASTROUTE_TCL FILL_CELLS FILL_CONFIG GDS_FILES GENERATE_ARTIFACTS_ON_FAILURE GLOBAL_PLACEMENT_ARGS GND_NETS_VOLTAGES GUI_NO_TIMING IR_DROP_LAYER KLAYOUT_TECH_FILE LIB_FILES MACRO_EXTENSION MAX_ROUTING_LAYER MIN_ROUTING_LAYER PLACE_DENSITY_LB_ADDON PLATFORM PRESERVE_CELLS PROCESS PWR_NETS_VOLTAGES RCX_RULES RECOVER_POWER REPAIR_PDN_VIA_LAYER ROUTING_LAYER_ADJUSTMENT SC_LEF SDC_FILE SEAL_GDS SET_RC_TCL SKIP_INCREMENTAL_REPAIR SKIP_REPORT_METRICS SLEW_MARGIN SYNTH_ARGS TAP_CELL_NAME TECH_LEF TNS_END_PERCENT USE_FILL
+CELL_PAD_IN_SITES_DETAIL_PLACEMENT DETAILED_METRICS MAX_ROUTING_LAYER MIN_ROUTING_LAYER ROUTING_LAYER_ADJUSTMENT TNS_END_PERCENT
 
-## route
+## route variables
 
-ADDITIONAL_FILES ADDITIONAL_GDS ADDITIONAL_LEFS ADDITIONAL_LIBS BLOCKS CAP_MARGIN CDL_FILES CORNER DESIGN_NAME DESIGN_NICKNAME DETAILED_ROUTE_ARGS DETAILED_ROUTE_END_ITERATION DFF_LIB_FILES DONT_USE_CELLS DONT_USE_LIBS DPO_MAX_DISPLACEMENT ENABLE_DPO FASTROUTE_TCL FILL_CELLS FILL_CONFIG GDS_FILES GENERATE_ARTIFACTS_ON_FAILURE GLOBAL_PLACEMENT_ARGS GND_NETS_VOLTAGES GUI_NO_TIMING IR_DROP_LAYER KLAYOUT_TECH_FILE LIB_FILES MACRO_EXTENSION MAX_ROUTING_LAYER MIN_ROUTING_LAYER PLACE_DENSITY_LB_ADDON PLATFORM PRESERVE_CELLS PROCESS PWR_NETS_VOLTAGES RCX_RULES RECOVER_POWER REPAIR_PDN_VIA_LAYER ROUTING_LAYER_ADJUSTMENT SC_LEF SDC_FILE SEAL_GDS SET_RC_TCL SKIP_INCREMENTAL_REPAIR SKIP_REPORT_METRICS SLEW_MARGIN SYNTH_ARGS TAP_CELL_NAME TECH_LEF USE_FILL
+DETAILED_ROUTE_ARGS DETAILED_ROUTE_END_ITERATION MAX_ROUTING_LAYER MIN_ROUTING_LAYER ROUTING_LAYER_ADJUSTMENT
 
-## final
+## final variables
 
-ADDITIONAL_FILES ADDITIONAL_GDS ADDITIONAL_LEFS ADDITIONAL_LIBS BLOCKS CAP_MARGIN CDL_FILES CORNER DESIGN_NAME DESIGN_NICKNAME DFF_LIB_FILES DONT_USE_CELLS DONT_USE_LIBS DPO_MAX_DISPLACEMENT ENABLE_DPO FASTROUTE_TCL FILL_CELLS FILL_CONFIG GDS_FILES GENERATE_ARTIFACTS_ON_FAILURE GLOBAL_PLACEMENT_ARGS GND_NETS_VOLTAGES GUI_NO_TIMING IR_DROP_LAYER KLAYOUT_TECH_FILE LIB_FILES MACRO_EXTENSION PLACE_DENSITY_LB_ADDON PLATFORM PRESERVE_CELLS PROCESS PWR_NETS_VOLTAGES RCX_RULES RECOVER_POWER REPAIR_PDN_VIA_LAYER ROUTING_LAYER_ADJUSTMENT SC_LEF SDC_FILE SEAL_GDS SET_RC_TCL SKIP_INCREMENTAL_REPAIR SKIP_REPORT_METRICS SLEW_MARGIN SYNTH_ARGS TAP_CELL_NAME TECH_LEF USE_FILL
+ROUTING_LAYER_ADJUSTMENT
 

flow/scripts/variables.py flow/scripts/generate-variables-docs.pyflow/scripts/variables.py renamed to flow/scripts/generate-variables-docs.py

@@ -1,4 +1,9 @@
 #!/usr/bin/env python3
+# variables.yaml is the single source of truth w.r.t. metainformation about
+# the ORFS variables.
+#
+# This script injects an autogenerated section in FlowVariables.md with
+# information about the variables from variables.yaml.
 import os
 import yaml
 
@@ -40,11 +45,11 @@
 markdown_table += table_header + table_rows
 
 for stage in stages:
-    markdown_table += f"## {stage}\n\n"
+    markdown_table += f"## {stage} variables\n\n"
     stage_keys = [
         key
         for key in sorted(data)
-        if "stages" not in data[key] or stage in data[key]["stages"]
+        if "stages" in data[key] and stage in data[key]["stages"]
     ]
     markdown_table += " ".join(stage_keys) + "\n\n"
 

flow/scripts/stage_variables.py flow/scripts/non_stage_variables.pyflow/scripts/stage_variables.py renamed to flow/scripts/non_stage_variables.py

@@ -1,5 +1,10 @@
 #!/usr/bin/env python3
-
+#
+# Reading .yaml from tcl is tedious and we already have
+# a yaml library in Python.
+#
+# This script generates a list of variables known
+# not to be in the current stage.
 import os
 import sys
 import yaml

flow/scripts/util.tcl

@@ -107,7 +107,7 @@ proc erase_non_stage_variables {stage_name} {
   # Tcl yaml package can't be imported in the sta/openroad environment:
   # 
   # https://github.com/The-OpenROAD-Project/OpenROAD/issues/5875
-  set variables [exec $::env(SCRIPTS_DIR)/stage_variables.py $stage_name]
+  set variables [exec $::env(SCRIPTS_DIR)/non_stage_variables.py $stage_name]
   foreach var $variables {
     if {[info exists ::env($var)]} {
       unset ::env($var)