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PDN_CFG --> PDN_TCL
Signed-off-by: vijayank88 <[email protected]>
1 parent 3d335be commit ad104f1

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12 files changed

+30
-207
lines changed

12 files changed

+30
-207
lines changed

flow/Makefile

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@@ -471,7 +471,7 @@ $(RESULTS_DIR)/2_5_floorplan_tapcell.odb: $(RESULTS_DIR)/2_4_floorplan_macro.odb
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# STEP 6: PDN generation
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#-------------------------------------------------------------------------------
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$(RESULTS_DIR)/2_6_floorplan_pdn.odb: $(RESULTS_DIR)/2_5_floorplan_tapcell.odb $(PDN_CFG) $(PDN_TCL)
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$(RESULTS_DIR)/2_6_floorplan_pdn.odb: $(RESULTS_DIR)/2_5_floorplan_tapcell.odb $(PDN_TCL)
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($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/pdn.tcl -metrics $(LOG_DIR)/2_6_pdn.json) 2>&1 | tee $(LOG_DIR)/2_6_pdn.log
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$(RESULTS_DIR)/2_floorplan.odb: $(RESULTS_DIR)/2_6_floorplan_pdn.odb
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####################################
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# global connections
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####################################
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add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power
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add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDPE$}
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add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDCE$}
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add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VPWR}
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add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VPB}
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add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground
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add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSSE$}
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add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VGND}
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add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VNB}
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global_connect
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####################################
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# voltage domains
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####################################
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set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
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####################################
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# standard cell grid
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####################################
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define_pdn_grid -name {grid} -voltage_domains {CORE}
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add_pdn_stripe -grid {grid} -layer {met1} -width {0.48} -pitch {5.44} -offset {0} -followpins
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add_pdn_stripe -grid {grid} -layer {met4} -width {1.600} -pitch {27.140} -offset {13.570}
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add_pdn_connect -grid {grid} -layers {met1 met4}

flow/designs/sky130hd/chameleon_hier/DFFRAM_4K/config.mk

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@@ -13,7 +13,7 @@ export VERILOG_FILES = \
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export SDC_FILE = ${TOP_DIR}/${DESIGN_NAME}/constraint.sdc
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export PDN_CFG = ${TOP_DIR}/${DESIGN_NAME}/pdn.cfg
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export PDN_TCL = ${TOP_DIR}/BLOCKS_pdn.tcl
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export ABC_DRIVER_CELL = sky130_fd_sc_hd__buf_1
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export ABC_LOAD_IN_FF = 3

flow/designs/sky130hd/chameleon_hier/DFFRAM_4K/pdn.cfg

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This file was deleted.

flow/designs/sky130hd/chameleon_hier/DMC_32x16HC/config.mk

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@@ -13,7 +13,7 @@ export VERILOG_FILES = \
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export SDC_FILE = ${TOP_DIR}/${DESIGN_NAME}/constraint.sdc
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export PDN_CFG = ${TOP_DIR}/${DESIGN_NAME}/pdn.cfg
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export PDN_TCL = ${TOP_DIR}/BLOCKS_pdn.tcl
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export ABC_DRIVER_CELL = sky130_fd_sc_hd__buf_1
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export ABC_LOAD_IN_FF = 3

flow/designs/sky130hd/chameleon_hier/DMC_32x16HC/pdn.cfg

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flow/designs/sky130hd/chameleon_hier/apb_sys_0/config.mk

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@@ -13,7 +13,7 @@ export VERILOG_FILES = \
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export SDC_FILE = ${TOP_DIR}/${DESIGN_NAME}/constraint.sdc
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export PDN_CFG = ${TOP_DIR}/${DESIGN_NAME}/pdn.cfg
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export PDN_TCL = ${TOP_DIR}/BLOCKS_pdn.tcl
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export ABC_DRIVER_CELL = sky130_fd_sc_hd__buf_1
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export ABC_LOAD_IN_FF = 3

flow/designs/sky130hd/chameleon_hier/apb_sys_0/pdn.cfg

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This file was deleted.

flow/designs/sky130hd/chameleon_hier/config.mk

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@@ -43,18 +43,13 @@ export VERILOG_FILES = \
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export HAS_IO_CONSTRAINTS = 1
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export ENABLE_DPO = 0
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export MACRO_PLACE_CHANNEL = 160 160
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export MACRO_PLACE_HALO = 160 160
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export MACRO_PLACE_HALO = 120 120
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export DIE_AREA = 0.0 0.0 6800 6800
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export CORE_AREA = 200 200 6600 6600
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export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
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export PDN_CFG = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/pdn.cfg
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export FP_PDN_RAIL_WIDTH = 0.48
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export FP_PDN_RAIL_OFFSET = 0
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export MIN_ROUTING_LAYER = met1
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export MAX_ROUTING_LAYER = met5
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export PWR_NETS_VOLTAGES = ""
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export GND_NETS_VOLTAGES = ""

flow/designs/sky130hd/chameleon_hier/ibex_wrapper/config.mk

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@@ -35,7 +35,7 @@ export VERILOG_FILES = \
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export SDC_FILE = ${TOP_DIR}/${DESIGN_NAME}/constraint.sdc
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export PDN_CFG = ${TOP_DIR}/${DESIGN_NAME}/pdn.cfg
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export PDN_TCL = ${TOP_DIR}/BLOCKS_pdn.tcl
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export ABC_DRIVER_CELL = sky130_fd_sc_hd__buf_1
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export ABC_LOAD_IN_FF = 3

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