Merge remote-tracking branch 'origin/master' into secure_hier_rtlmp

Signed-off-by: Ravi Varadarajan <[email protected]>

Author: ravi-varadarajan

.gitignore

@@ -59,6 +59,7 @@ flow/platforms/*
 !flow/platforms/sky130hs
 !flow/platforms/sky130io
 !flow/platforms/sky130ram
+!flow/platforms/gf180
 flow/private
 
 # network

flow/Makefile

@@ -75,6 +75,8 @@
 
 # DESIGN_CONFIG=./designs/intel22/gcd/config.mk
 # DESIGN_CONFIG=./designs/intel22/aes/config.mk
+
+# DESIGN_CONFIG=./designs/gf180/aes/config.mk
 #
 # Default design
 DESIGN_CONFIG ?= ./designs/nangate45/gcd/config.mk
@@ -582,6 +584,10 @@ $(RESULTS_DIR)/5_route.odb: $(RESULTS_DIR)/5_2_route.odb
 $(RESULTS_DIR)/5_route.sdc: $(RESULTS_DIR)/4_cts.sdc
 	cp $< $@
 
+$(RESULTS_DIR)/5_route.v:
+	@export OR_DB=5_route ;\
+	$(OPENROAD_CMD) ./scripts/write_verilog.tcl
+
 clean_route:
 	rm -rf output*/ results*.out.dmp layer_*.mps
 	rm -rf *.gdid *.log *.met *.sav *.res.dmp

flow/designs/gf180/aes/config.mk

@@ -0,0 +1,19 @@
+export DESIGN_NICKNAME = aes
+export DESIGN_NAME     = aes_cipher_top
+export PLATFORM        = gf180
+
+export VERILOG_FILES   = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
+export SDC_FILE        = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
+export ABC_AREA        = 1
+
+export CORE_UTILIZATION  = 35
+export CORE_ASPECT_RATIO = 1
+export CORE_MARGIN       = 2
+
+export PLACE_DENSITY = 0.60
+
+ifneq ($(USE_FILL),)
+export DESIGN_TYPE = CELL
+else
+export DESIGN_TYPE = CELL_NODEN
+endif

flow/designs/gf180/aes/constraint.sdc

@@ -0,0 +1,19 @@
+current_design aes_cipher_top
+
+set clk_name  clk
+set clk_port_name clk
+set clk_period 60
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period  $clk_port
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+
+set_input_delay  [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs 
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
+
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+

flow/designs/gf180/aes/metadata-base-ok.json

@@ -0,0 +1,286 @@
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+}