variables: fix TIE_SEPARATION

it is used only from floorplan and was ignored as it was listed
as place only in variables.yaml

added default value, less brittle

Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

docs/user/FlowVariables.md

@@ -238,7 +238,7 @@ configuration file.
 | <a name="TECH_LEF"></a>TECH_LEF| A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.| |
 | <a name="TIEHI_CELL_AND_PORT"></a>TIEHI_CELL_AND_PORT| Tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist.| |
 | <a name="TIELO_CELL_AND_PORT"></a>TIELO_CELL_AND_PORT| Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.| |
-| <a name="TIE_SEPARATION"></a>TIE_SEPARATION| Distance separating tie high/low instances from the load.| |
+| <a name="TIE_SEPARATION"></a>TIE_SEPARATION| Distance separating tie high/low instances from the load.| 0|
 | <a name="TNS_END_PERCENT"></a>TNS_END_PERCENT| Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed.| 100|
 | <a name="USE_FILL"></a>USE_FILL| Whether to perform metal density filling.| 0|
 | <a name="VERILOG_DEFINES"></a>VERILOG_DEFINES| Preprocessor defines passed to the language frontend. Example: `-D HPDCACHE_ASSERT_OFF`| |
@@ -331,6 +331,7 @@ configuration file.
 - [TAPCELL_TCL](#TAPCELL_TCL)
 - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
 - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)
+- [TIE_SEPARATION](#TIE_SEPARATION)
 - [TNS_END_PERCENT](#TNS_END_PERCENT)
 
 ## place variables
@@ -353,7 +354,6 @@ configuration file.
 - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT)
 - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
 - [SWAP_ARITH_OPERATORS](#SWAP_ARITH_OPERATORS)
-- [TIE_SEPARATION](#TIE_SEPARATION)
 
 ## cts variables
 

flow/scripts/util.tcl

@@ -14,25 +14,19 @@ proc log_cmd { cmd args } {
 }
 
 proc repair_tie_fanout_helper { } {
-  if { [env_var_exists_and_non_empty TIE_SEPARATION] } {
-    set tie_separation $env(TIE_SEPARATION)
-  } else {
-    set tie_separation 0
-  }
-
   # Repair tie lo fanout
   puts "Repair tie lo fanout..."
   set tielo_cell_name [lindex $::env(TIELO_CELL_AND_PORT) 0]
   set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]]
   set tielo_pin $tielo_lib_name/$tielo_cell_name/[lindex $::env(TIELO_CELL_AND_PORT) 1]
-  repair_tie_fanout -separation $tie_separation $tielo_pin
+  repair_tie_fanout -separation $::env(TIE_SEPARATION) $tielo_pin
 
   # Repair tie hi fanout
   puts "Repair tie hi fanout..."
   set tiehi_cell_name [lindex $::env(TIEHI_CELL_AND_PORT) 0]
   set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]]
   set tiehi_pin $tiehi_lib_name/$tiehi_cell_name/[lindex $::env(TIEHI_CELL_AND_PORT) 1]
-  repair_tie_fanout -separation $tie_separation $tiehi_pin
+  repair_tie_fanout -separation $::env(TIE_SEPARATION) $tiehi_pin
 }
 
 proc fast_route { } {

flow/scripts/variables.yaml

@@ -232,7 +232,8 @@ TIE_SEPARATION:
   description: |
     Distance separating tie high/low instances from the load.
   stages:
-    - place
+    - floorplan
+  default: 0
 EARLY_SIZING_CAP_RATIO:
   description: |
     Ratio between the input pin capacitance and the output pin load during initial gate sizing.