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Merge pull request #943 from The-OpenROAD-Project-staging/secure-flow3
Secure flow3 (add new designs ariane133 for NG45 and gf12)
2 parents 18087e3 + eac75f9 commit adbb3a3

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set sdc_version 2.0
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set_units -capacitance 1fF
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set_units -time 1ps
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# Set the current design
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current_design ariane
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create_clock -name "core_clock" -period 1800.0 -waveform {0.0 900.0} [get_ports clk_i]
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set_clock_gating_check -setup 0.0
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set_wire_load_mode "top"
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export DESIGN_NICKNAME = ariane133
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export DESIGN_NAME = ariane
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export PLATFORM = gf12
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export SYNTH_HIERARCHICAL = 1
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export MAX_UNGROUP_SIZE ?= 1000
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export RTLMP_FLOW = True
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#
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# RTL_MP Settings
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export RTLMP_MAX_INST = 20000
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export RTLMP_MIN_INST = 4000
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export RTLMP_MAX_MACRO = 12
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export RTLMP_MIN_MACRO = 4
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export VERILOG_FILES = $(PLATFORM_DIR)/ariane133/ariane.v
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export SDC_FILE = ./designs/$(PLATFORM)/ariane133/ariane.sdc
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export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1rw_256x16.lef
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export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1rw_256x16_ffpg_sigcmin_0p88v_0p88v_m40c.lib
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export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12lp_1rf_lg8_w64_byte.gds2
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export DIE_AREA = 0 0 800 600
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export CORE_AREA = 2 2 800 600
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export PLACE_PINS_ARGS = -exclude left:0-250 -exclude left:500-600 -exclude right:* -exclude top:* -exclude bottom:*
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export MACRO_PLACE_HALO = 4 4
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export MACRO_PLACE_CHANNEL = 8 8
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export PLACE_DENSITY_LB_ADDON = 0.02
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ifneq ($(USE_FILL),)
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export DESIGN_TYPE = CELL
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else
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export DESIGN_TYPE = CELL_NODEN
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endif
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{
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"constraints__clocks__count": 1,
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"constraints__clocks__details": [
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"core_clock: 1800.0000"
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],
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}

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