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Merge remote-tracking branch 'origin/master' into secure-remove-wrappers
Signed-off-by: Osama <[email protected]>
2 parents 8295144 + 4487b09 commit afc93db

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flow/Makefile

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -437,7 +437,7 @@ synth-report: synth
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.PHONY: do-synth-report
439439
do-synth-report:
440-
($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/synth_metrics.tcl) 2>&1 | tee $(LOG_DIR)/1_1_yosys_metrics.log
440+
($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/synth_metrics.tcl) 2>&1 | tee $(abspath $(LOG_DIR)/1_1_yosys_metrics.log)
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442442
.PHONY: memory
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memory:
@@ -860,7 +860,7 @@ generate_abstract: $(RESULTS_DIR)/6_final.gds $(RESULTS_DIR)/6_final.def $(RESU
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.PHONY: do-generate_abstract
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do-generate_abstract:
862862
mkdir -p $(LOG_DIR) $(REPORTS_DIR)
863-
($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/generate_abstract.tcl -metrics $(LOG_DIR)/generate_abstract.json) 2>&1 | tee $(LOG_DIR)/generate_abstract.log
863+
($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/generate_abstract.tcl -metrics $(LOG_DIR)/generate_abstract.json) 2>&1 | tee $(abspath $(LOG_DIR)/generate_abstract.log)
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865865
.PHONY: clean_abstract
866866
clean_abstract:
@@ -878,7 +878,7 @@ $(WRAPPED_GDSOAS): $(OBJECTS_DIR)/klayout_wrap.lyt $(WRAPPED_LEFS)
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-rd out_file=$@ \
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-rd tech_file=$(OBJECTS_DIR)/klayout_wrap.lyt \
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-rd layer_map=$(GDS_LAYER_MAP) \
881-
-r $(UTILS_DIR)/def2stream.py) 2>&1 | tee $(LOG_DIR)/6_merge_$(basename $(notdir $@)).log
881+
-r $(UTILS_DIR)/def2stream.py) 2>&1 | tee $(abspath $(LOG_DIR)/6_merge_$(basename $(notdir $@)).log)
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883883
# Merge GDS using Klayout
884884
#-------------------------------------------------------------------------------
@@ -896,7 +896,7 @@ do-gds-merged:
896896
-rd out_file=$(GDS_MERGED_FILE) \
897897
-rd tech_file=$(OBJECTS_DIR)/klayout.lyt \
898898
-rd layer_map=$(GDS_LAYER_MAP) \
899-
-r $(UTILS_DIR)/def2stream.py) 2>&1 | tee $(LOG_DIR)/6_1_merge.log
899+
-r $(UTILS_DIR)/def2stream.py) 2>&1 | tee $(abspath $(LOG_DIR)/6_1_merge.log)
900900

901901
$(RESULTS_DIR)/6_final.v: $(LOG_DIR)/6_report.log
902902

@@ -916,15 +916,15 @@ ifneq ($(KLAYOUT_DRC_FILE),)
916916
$(call KLAYOUT_FOUND)
917917
($(TIME_CMD) $(KLAYOUT_CMD) -zz -rd in_gds="$<" \
918918
-rd report_file=$(abspath $@) \
919-
-r $(KLAYOUT_DRC_FILE)) 2>&1 | tee $(LOG_DIR)/6_drc.log
919+
-r $(KLAYOUT_DRC_FILE)) 2>&1 | tee $(abspath $(LOG_DIR)/6_drc.log)
920920
# Hacky way of getting DRV count (don't error on no matches)
921921
grep -c "<value>" $@ > $(REPORTS_DIR)/6_drc_count.rpt || [[ $$? == 1 ]]
922922
else
923923
echo "DRC not supported on this platform" > $@
924924
endif
925925

926926
$(RESULTS_DIR)/6_final.cdl: $(RESULTS_DIR)/6_final.v
927-
($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/cdl.tcl) 2>&1 | tee $(LOG_DIR)/6_cdl.log
927+
($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/cdl.tcl) 2>&1 | tee $(abspath $(LOG_DIR)/6_cdl.log)
928928

929929
$(OBJECTS_DIR)/6_final_concat.cdl: $(RESULTS_DIR)/6_final.cdl $(CDL_FILE)
930930
cat $^ > $@
@@ -938,7 +938,7 @@ ifneq ($(KLAYOUT_LVS_FILE),)
938938
($(TIME_CMD) $(KLAYOUT_CMD) -b -rd in_gds="$<" \
939939
-rd cdl_file=$(abspath $(OBJECTS_DIR)/6_final_concat.cdl) \
940940
-rd report_file=$(abspath $@) \
941-
-r $(KLAYOUT_LVS_FILE)) 2>&1 | tee $(LOG_DIR)/6_lvs.log
941+
-r $(KLAYOUT_LVS_FILE)) 2>&1 | tee $(abspath $(LOG_DIR)/6_lvs.log)
942942
else
943943
echo "LVS not supported on this platform" > $@
944944
endif

flow/scripts/variables.yaml

Lines changed: 36 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -211,8 +211,8 @@ FLOORPLAN_DEF:
211211
REMOVE_ABC_BUFFERS:
212212
description: >
213213
Remove abc buffers from the netlist. If timing repair in floorplanning is
214-
taking too long, use a SETUP_HOLD_MARGIN to terminate timing repair early
215-
instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GAST=1.
214+
taking too long, use a SETUP/HOLD_SLACK_MARGIN to terminate timing repair early
215+
instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GASP=1.
216216
stages:
217217
- floorplan
218218
deprecated: 1
@@ -384,16 +384,45 @@ HOLD_SLACK_MARGIN:
384384
This option allows you to overfix or underfix(negative value, terminate
385385
retiming before 0 or positive slack).
386386
387-
Use min of HOLD_SLACK_MARGIN and 0(default hold slack margin) in floorplan.
387+
floorplan.tcl uses min of HOLD_SLACK_MARGIN and 0(default hold slack margin).
388388
389389
This avoids overrepair in floorplan for hold by default, but allows skipping
390390
hold repair using a negative HOLD_SLACK_MARGIN.
391391
392392
Exiting timing repair early is useful in exploration where
393-
394-
the .sdc has a fixed clock period at designs target clock period and where
393+
the .sdc has a fixed clock period at the design's target clock period and where
395394
HOLD/SETUP_SLACK_MARGIN is used to avoid overrepair(extremely long running
396395
times) when exploring different parameter settings.
396+
397+
When an ideal clock is used, that is before CTS,
398+
a clock insertion delay of 0 is used in timing paths. This creates
399+
a mismatch between macros that have a .lib file from after CTS, when
400+
the clock is propagated. To mitigate this, OpenSTA will use subtract
401+
the clock insertion delay of macros when calculating timing with ideal
402+
clock. Provided that min_clock_tree_path
403+
and max_clock_tree_path are in the .lib file, which is the case for
404+
macros built with OpenROAD. This is less accurate than if OpenROAD had
405+
created a placeholder clock tree for timing estimation purposes
406+
prior to CTS.
407+
408+
There will inevitably be inaccuracies in the timing calculation prior
409+
to CTS. Use a slack margin that is low enough, even negative, to
410+
avoid overrepair. Inaccuracies in the timing prior to CTS can also
411+
lead to underrepair, but there no obvious and simple way to avoid
412+
underrapir in these cases.
413+
414+
Overrepair can lead to excessive runtimes in repair or too much buffering
415+
being added, which can present itself as congestion of hold cells or
416+
buffer cells.
417+
418+
Another use of SETUP/HOLD_SLACK_MARGIN is design parameter exploration
419+
when trying to find the minimum clock period for a design.
420+
421+
The SDC_FILE for a design can be quite complicated and instead of
422+
modifying the clock period in the SDC_FILE, which can be non-trivial,
423+
the clock period can be fixed at the target frequency and the
424+
SETUP/HOLD_SLACK_MARGIN can be swept to find a plausible
425+
current minimum clock period.
397426
stages:
398427
- cts
399428
- floorplan
@@ -404,6 +433,8 @@ SETUP_SLACK_MARGIN:
404433
Specifies a time margin for the slack when fixing setup violations.
405434
This option allows you to overfix or underfix(negative value, terminate
406435
retiming before 0 or positive slack).
436+
437+
See HOLD_SLACK_MARGIN for more details.
407438
stages:
408439
- cts
409440
- floorplan

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