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mock-array: register io_lsbs_* outputs in preparation for 500ps
Signed-off-by: Øyvind Harboe <[email protected]>
1 parent 0d97930 commit b05d2b7

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2 files changed

+195
-65
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2 files changed

+195
-65
lines changed

‎flow/designs/src/mock-array/MockArray.v‎

Lines changed: 194 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -1666,6 +1666,70 @@ module MockArray(
16661666
wire ces_7_7_io_lsbOuts_5;
16671667
wire ces_7_7_io_lsbOuts_6;
16681668
wire ces_7_7_io_lsbOuts_7;
1669+
reg REG_0;
1670+
reg REG_1;
1671+
reg REG_2;
1672+
reg REG_3;
1673+
reg REG_4;
1674+
reg REG_5;
1675+
reg REG_6;
1676+
reg REG_7;
1677+
reg REG_8;
1678+
reg REG_9;
1679+
reg REG_10;
1680+
reg REG_11;
1681+
reg REG_12;
1682+
reg REG_13;
1683+
reg REG_14;
1684+
reg REG_15;
1685+
reg REG_16;
1686+
reg REG_17;
1687+
reg REG_18;
1688+
reg REG_19;
1689+
reg REG_20;
1690+
reg REG_21;
1691+
reg REG_22;
1692+
reg REG_23;
1693+
reg REG_24;
1694+
reg REG_25;
1695+
reg REG_26;
1696+
reg REG_27;
1697+
reg REG_28;
1698+
reg REG_29;
1699+
reg REG_30;
1700+
reg REG_31;
1701+
reg REG_32;
1702+
reg REG_33;
1703+
reg REG_34;
1704+
reg REG_35;
1705+
reg REG_36;
1706+
reg REG_37;
1707+
reg REG_38;
1708+
reg REG_39;
1709+
reg REG_40;
1710+
reg REG_41;
1711+
reg REG_42;
1712+
reg REG_43;
1713+
reg REG_44;
1714+
reg REG_45;
1715+
reg REG_46;
1716+
reg REG_47;
1717+
reg REG_48;
1718+
reg REG_49;
1719+
reg REG_50;
1720+
reg REG_51;
1721+
reg REG_52;
1722+
reg REG_53;
1723+
reg REG_54;
1724+
reg REG_55;
1725+
reg REG_56;
1726+
reg REG_57;
1727+
reg REG_58;
1728+
reg REG_59;
1729+
reg REG_60;
1730+
reg REG_61;
1731+
reg REG_62;
1732+
reg REG_63;
16691733
Element ces_0_0 (
16701734
.clock(ces_0_0_clock),
16711735
.io_ins_down(ces_0_0_io_ins_down),
@@ -3362,70 +3426,70 @@ module MockArray(
33623426
assign io_outsDown_5 = ces_0_5_io_outs_down;
33633427
assign io_outsDown_6 = ces_0_6_io_outs_down;
33643428
assign io_outsDown_7 = ces_0_7_io_outs_down;
3365-
assign io_lsbs_0 = ces_0_7_io_lsbOuts_0;
3366-
assign io_lsbs_1 = ces_0_7_io_lsbOuts_1;
3367-
assign io_lsbs_2 = ces_0_7_io_lsbOuts_2;
3368-
assign io_lsbs_3 = ces_0_7_io_lsbOuts_3;
3369-
assign io_lsbs_4 = ces_0_7_io_lsbOuts_4;
3370-
assign io_lsbs_5 = ces_0_7_io_lsbOuts_5;
3371-
assign io_lsbs_6 = ces_0_7_io_lsbOuts_6;
3372-
assign io_lsbs_7 = ces_0_7_io_lsbOuts_7;
3373-
assign io_lsbs_8 = ces_1_7_io_lsbOuts_0;
3374-
assign io_lsbs_9 = ces_1_7_io_lsbOuts_1;
3375-
assign io_lsbs_10 = ces_1_7_io_lsbOuts_2;
3376-
assign io_lsbs_11 = ces_1_7_io_lsbOuts_3;
3377-
assign io_lsbs_12 = ces_1_7_io_lsbOuts_4;
3378-
assign io_lsbs_13 = ces_1_7_io_lsbOuts_5;
3379-
assign io_lsbs_14 = ces_1_7_io_lsbOuts_6;
3380-
assign io_lsbs_15 = ces_1_7_io_lsbOuts_7;
3381-
assign io_lsbs_16 = ces_2_7_io_lsbOuts_0;
3382-
assign io_lsbs_17 = ces_2_7_io_lsbOuts_1;
3383-
assign io_lsbs_18 = ces_2_7_io_lsbOuts_2;
3384-
assign io_lsbs_19 = ces_2_7_io_lsbOuts_3;
3385-
assign io_lsbs_20 = ces_2_7_io_lsbOuts_4;
3386-
assign io_lsbs_21 = ces_2_7_io_lsbOuts_5;
3387-
assign io_lsbs_22 = ces_2_7_io_lsbOuts_6;
3388-
assign io_lsbs_23 = ces_2_7_io_lsbOuts_7;
3389-
assign io_lsbs_24 = ces_3_7_io_lsbOuts_0;
3390-
assign io_lsbs_25 = ces_3_7_io_lsbOuts_1;
3391-
assign io_lsbs_26 = ces_3_7_io_lsbOuts_2;
3392-
assign io_lsbs_27 = ces_3_7_io_lsbOuts_3;
3393-
assign io_lsbs_28 = ces_3_7_io_lsbOuts_4;
3394-
assign io_lsbs_29 = ces_3_7_io_lsbOuts_5;
3395-
assign io_lsbs_30 = ces_3_7_io_lsbOuts_6;
3396-
assign io_lsbs_31 = ces_3_7_io_lsbOuts_7;
3397-
assign io_lsbs_32 = ces_4_7_io_lsbOuts_0;
3398-
assign io_lsbs_33 = ces_4_7_io_lsbOuts_1;
3399-
assign io_lsbs_34 = ces_4_7_io_lsbOuts_2;
3400-
assign io_lsbs_35 = ces_4_7_io_lsbOuts_3;
3401-
assign io_lsbs_36 = ces_4_7_io_lsbOuts_4;
3402-
assign io_lsbs_37 = ces_4_7_io_lsbOuts_5;
3403-
assign io_lsbs_38 = ces_4_7_io_lsbOuts_6;
3404-
assign io_lsbs_39 = ces_4_7_io_lsbOuts_7;
3405-
assign io_lsbs_40 = ces_5_7_io_lsbOuts_0;
3406-
assign io_lsbs_41 = ces_5_7_io_lsbOuts_1;
3407-
assign io_lsbs_42 = ces_5_7_io_lsbOuts_2;
3408-
assign io_lsbs_43 = ces_5_7_io_lsbOuts_3;
3409-
assign io_lsbs_44 = ces_5_7_io_lsbOuts_4;
3410-
assign io_lsbs_45 = ces_5_7_io_lsbOuts_5;
3411-
assign io_lsbs_46 = ces_5_7_io_lsbOuts_6;
3412-
assign io_lsbs_47 = ces_5_7_io_lsbOuts_7;
3413-
assign io_lsbs_48 = ces_6_7_io_lsbOuts_0;
3414-
assign io_lsbs_49 = ces_6_7_io_lsbOuts_1;
3415-
assign io_lsbs_50 = ces_6_7_io_lsbOuts_2;
3416-
assign io_lsbs_51 = ces_6_7_io_lsbOuts_3;
3417-
assign io_lsbs_52 = ces_6_7_io_lsbOuts_4;
3418-
assign io_lsbs_53 = ces_6_7_io_lsbOuts_5;
3419-
assign io_lsbs_54 = ces_6_7_io_lsbOuts_6;
3420-
assign io_lsbs_55 = ces_6_7_io_lsbOuts_7;
3421-
assign io_lsbs_56 = ces_7_7_io_lsbOuts_0;
3422-
assign io_lsbs_57 = ces_7_7_io_lsbOuts_1;
3423-
assign io_lsbs_58 = ces_7_7_io_lsbOuts_2;
3424-
assign io_lsbs_59 = ces_7_7_io_lsbOuts_3;
3425-
assign io_lsbs_60 = ces_7_7_io_lsbOuts_4;
3426-
assign io_lsbs_61 = ces_7_7_io_lsbOuts_5;
3427-
assign io_lsbs_62 = ces_7_7_io_lsbOuts_6;
3428-
assign io_lsbs_63 = ces_7_7_io_lsbOuts_7;
3429+
assign io_lsbs_0 = REG_0;
3430+
assign io_lsbs_1 = REG_1;
3431+
assign io_lsbs_2 = REG_2;
3432+
assign io_lsbs_3 = REG_3;
3433+
assign io_lsbs_4 = REG_4;
3434+
assign io_lsbs_5 = REG_5;
3435+
assign io_lsbs_6 = REG_6;
3436+
assign io_lsbs_7 = REG_7;
3437+
assign io_lsbs_8 = REG_8;
3438+
assign io_lsbs_9 = REG_9;
3439+
assign io_lsbs_10 = REG_10;
3440+
assign io_lsbs_11 = REG_11;
3441+
assign io_lsbs_12 = REG_12;
3442+
assign io_lsbs_13 = REG_13;
3443+
assign io_lsbs_14 = REG_14;
3444+
assign io_lsbs_15 = REG_15;
3445+
assign io_lsbs_16 = REG_16;
3446+
assign io_lsbs_17 = REG_17;
3447+
assign io_lsbs_18 = REG_18;
3448+
assign io_lsbs_19 = REG_19;
3449+
assign io_lsbs_20 = REG_20;
3450+
assign io_lsbs_21 = REG_21;
3451+
assign io_lsbs_22 = REG_22;
3452+
assign io_lsbs_23 = REG_23;
3453+
assign io_lsbs_24 = REG_24;
3454+
assign io_lsbs_25 = REG_25;
3455+
assign io_lsbs_26 = REG_26;
3456+
assign io_lsbs_27 = REG_27;
3457+
assign io_lsbs_28 = REG_28;
3458+
assign io_lsbs_29 = REG_29;
3459+
assign io_lsbs_30 = REG_30;
3460+
assign io_lsbs_31 = REG_31;
3461+
assign io_lsbs_32 = REG_32;
3462+
assign io_lsbs_33 = REG_33;
3463+
assign io_lsbs_34 = REG_34;
3464+
assign io_lsbs_35 = REG_35;
3465+
assign io_lsbs_36 = REG_36;
3466+
assign io_lsbs_37 = REG_37;
3467+
assign io_lsbs_38 = REG_38;
3468+
assign io_lsbs_39 = REG_39;
3469+
assign io_lsbs_40 = REG_40;
3470+
assign io_lsbs_41 = REG_41;
3471+
assign io_lsbs_42 = REG_42;
3472+
assign io_lsbs_43 = REG_43;
3473+
assign io_lsbs_44 = REG_44;
3474+
assign io_lsbs_45 = REG_45;
3475+
assign io_lsbs_46 = REG_46;
3476+
assign io_lsbs_47 = REG_47;
3477+
assign io_lsbs_48 = REG_48;
3478+
assign io_lsbs_49 = REG_49;
3479+
assign io_lsbs_50 = REG_50;
3480+
assign io_lsbs_51 = REG_51;
3481+
assign io_lsbs_52 = REG_52;
3482+
assign io_lsbs_53 = REG_53;
3483+
assign io_lsbs_54 = REG_54;
3484+
assign io_lsbs_55 = REG_55;
3485+
assign io_lsbs_56 = REG_56;
3486+
assign io_lsbs_57 = REG_57;
3487+
assign io_lsbs_58 = REG_58;
3488+
assign io_lsbs_59 = REG_59;
3489+
assign io_lsbs_60 = REG_60;
3490+
assign io_lsbs_61 = REG_61;
3491+
assign io_lsbs_62 = REG_62;
3492+
assign io_lsbs_63 = REG_63;
34293493
assign ces_0_0_clock = clock;
34303494
assign ces_0_0_io_ins_down = ces_1_0_io_outs_down;
34313495
assign ces_0_0_io_ins_right = io_insRight_0;
@@ -4194,4 +4258,70 @@ module MockArray(
41944258
assign ces_7_7_io_lsbIns_5 = ces_7_6_io_lsbOuts_5;
41954259
assign ces_7_7_io_lsbIns_6 = ces_7_6_io_lsbOuts_6;
41964260
assign ces_7_7_io_lsbIns_7 = ces_7_6_io_lsbOuts_7;
4261+
always @(posedge clock) begin
4262+
REG_0 <= ces_0_7_io_lsbOuts_0;
4263+
REG_1 <= ces_0_7_io_lsbOuts_1;
4264+
REG_2 <= ces_0_7_io_lsbOuts_2;
4265+
REG_3 <= ces_0_7_io_lsbOuts_3;
4266+
REG_4 <= ces_0_7_io_lsbOuts_4;
4267+
REG_5 <= ces_0_7_io_lsbOuts_5;
4268+
REG_6 <= ces_0_7_io_lsbOuts_6;
4269+
REG_7 <= ces_0_7_io_lsbOuts_7;
4270+
REG_8 <= ces_1_7_io_lsbOuts_0;
4271+
REG_9 <= ces_1_7_io_lsbOuts_1;
4272+
REG_10 <= ces_1_7_io_lsbOuts_2;
4273+
REG_11 <= ces_1_7_io_lsbOuts_3;
4274+
REG_12 <= ces_1_7_io_lsbOuts_4;
4275+
REG_13 <= ces_1_7_io_lsbOuts_5;
4276+
REG_14 <= ces_1_7_io_lsbOuts_6;
4277+
REG_15 <= ces_1_7_io_lsbOuts_7;
4278+
REG_16 <= ces_2_7_io_lsbOuts_0;
4279+
REG_17 <= ces_2_7_io_lsbOuts_1;
4280+
REG_18 <= ces_2_7_io_lsbOuts_2;
4281+
REG_19 <= ces_2_7_io_lsbOuts_3;
4282+
REG_20 <= ces_2_7_io_lsbOuts_4;
4283+
REG_21 <= ces_2_7_io_lsbOuts_5;
4284+
REG_22 <= ces_2_7_io_lsbOuts_6;
4285+
REG_23 <= ces_2_7_io_lsbOuts_7;
4286+
REG_24 <= ces_3_7_io_lsbOuts_0;
4287+
REG_25 <= ces_3_7_io_lsbOuts_1;
4288+
REG_26 <= ces_3_7_io_lsbOuts_2;
4289+
REG_27 <= ces_3_7_io_lsbOuts_3;
4290+
REG_28 <= ces_3_7_io_lsbOuts_4;
4291+
REG_29 <= ces_3_7_io_lsbOuts_5;
4292+
REG_30 <= ces_3_7_io_lsbOuts_6;
4293+
REG_31 <= ces_3_7_io_lsbOuts_7;
4294+
REG_32 <= ces_4_7_io_lsbOuts_0;
4295+
REG_33 <= ces_4_7_io_lsbOuts_1;
4296+
REG_34 <= ces_4_7_io_lsbOuts_2;
4297+
REG_35 <= ces_4_7_io_lsbOuts_3;
4298+
REG_36 <= ces_4_7_io_lsbOuts_4;
4299+
REG_37 <= ces_4_7_io_lsbOuts_5;
4300+
REG_38 <= ces_4_7_io_lsbOuts_6;
4301+
REG_39 <= ces_4_7_io_lsbOuts_7;
4302+
REG_40 <= ces_5_7_io_lsbOuts_0;
4303+
REG_41 <= ces_5_7_io_lsbOuts_1;
4304+
REG_42 <= ces_5_7_io_lsbOuts_2;
4305+
REG_43 <= ces_5_7_io_lsbOuts_3;
4306+
REG_44 <= ces_5_7_io_lsbOuts_4;
4307+
REG_45 <= ces_5_7_io_lsbOuts_5;
4308+
REG_46 <= ces_5_7_io_lsbOuts_6;
4309+
REG_47 <= ces_5_7_io_lsbOuts_7;
4310+
REG_48 <= ces_6_7_io_lsbOuts_0;
4311+
REG_49 <= ces_6_7_io_lsbOuts_1;
4312+
REG_50 <= ces_6_7_io_lsbOuts_2;
4313+
REG_51 <= ces_6_7_io_lsbOuts_3;
4314+
REG_52 <= ces_6_7_io_lsbOuts_4;
4315+
REG_53 <= ces_6_7_io_lsbOuts_5;
4316+
REG_54 <= ces_6_7_io_lsbOuts_6;
4317+
REG_55 <= ces_6_7_io_lsbOuts_7;
4318+
REG_56 <= ces_7_7_io_lsbOuts_0;
4319+
REG_57 <= ces_7_7_io_lsbOuts_1;
4320+
REG_58 <= ces_7_7_io_lsbOuts_2;
4321+
REG_59 <= ces_7_7_io_lsbOuts_3;
4322+
REG_60 <= ces_7_7_io_lsbOuts_4;
4323+
REG_61 <= ces_7_7_io_lsbOuts_5;
4324+
REG_62 <= ces_7_7_io_lsbOuts_6;
4325+
REG_63 <= ces_7_7_io_lsbOuts_7;
4326+
end
41974327
endmodule

‎flow/designs/src/mock-array/src/test/scala/MockArray.scala‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,7 @@ class MockArray(width:Int, height:Int, singleElementWidth:Int) extends Module {
7373
}
7474
}}
7575

76-
io.lsbs := ces.map(_.last.io.lsbOuts).flatten
76+
io.lsbs := RegNext(VecInit(ces.map(_.last.io.lsbOuts).flatten))
7777

7878
// Connect inputs to edge element buses
7979
(ces.map(_.head).map(_.io.ins.asMap(Routes.RIGHT)) zip io.insRight).foreach { case (a, b) => a := b }

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