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Merge pull request #339 from The-OpenROAD-Project-staging/ol-asap7
Add files for preliminary openlane asap7 support
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‎flow/platforms/asap7/openlane/README‎

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This is for an experimental integration of OpenROAD-flow-scripts into
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OpenLane. These files are not used directly by ORFS.

‎flow/platforms/asap7/openlane/asap7sc7p5t/config.tcl‎

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set current_folder [file dirname [file normalize [info script]]]
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# Technology lib
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set libs_ref "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)"
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set libs_tech "$::env(PDK_ROOT)/$::env(PDK)/libs.tech"
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set ::env(LIB_FASTEST) ""
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set ::env(LIB_TYPICAL) ""
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set ::env(LIB_SLOWEST) ""
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set lib_path "$libs_ref/lib"
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foreach lib {"AO" "INVBUF" "OA" "SEQ" "SIMPLE"} {
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append ::env(LIB_FASTEST) "$lib_path/asap7sc7p5t_${lib}_RVT_FF_nldm_201020.lib "
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append ::env(LIB_TYPICAL) "$lib_path/asap7sc7p5t_${lib}_RVT_TT_nldm_201020.lib "
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append ::env(LIB_SLOWEST) "$lib_path/asap7sc7p5t_${lib}_RVT_SS_nldm_201020.lib "
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}
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set ::env(LIB_SYNTH) $::env(LIB_TYPICAL)
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set ::env(LIB_RESIZER_OPT) $::env(LIB_SYNTH)
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set ::env(DFF_LIB_SYNTH) "$lib_path/asap7sc7p5t_SEQ_RVT_TT_nldm_201020.lib"
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set ::env(LIB_CTS) $::env(LIB_TYPICAL)
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# Placement site for core cells
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# This can be found in the technology lef
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set ::env(PLACE_SITE) "asap7sc7p5t"
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set ::env(PLACE_SITE_WIDTH) 0.054
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set ::env(PLACE_SITE_HEIGHT) 0.270
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# welltap and endcap cells
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set ::env(FP_WELLTAP_CELL) "TAPCELL_ASAP7_75t_R"
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set ::env(FP_ENDCAP_CELL) "TAPCELL_ASAP7_75t_R"
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# defaults (can be overridden by designs):
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set ::env(SYNTH_DRIVING_CELL) "BUFx2_ASAP7_75t_R"
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set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
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set ::env(SYNTH_CAP_LOAD) "4.61057" ; # femtofarad INVx8_ASAP7_75t_R pin A cap
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set ::env(SYNTH_MIN_BUF_PORT) "BUFx2_ASAP7_75t_R A Y"
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set ::env(SYNTH_TIEHI_PORT) "TIEHIx1_ASAP7_75t_R H"
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set ::env(SYNTH_TIELO_PORT) "TIELOx1_ASAP7_75t_R L"
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# cts defaults
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set ::env(CTS_ROOT_BUFFER) BUFx4_ASAP7_75t_R
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set ::env(CELL_CLK_PORT) CLK
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# Placement defaults
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set ::env(PL_LIB) $::env(LIB_TYPICAL)
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# Fillcell insertion
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set ::env(FILL_CELL) "FILLERxp5_ASAP7_75t_R"
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set ::env(DECAP_CELL) "DECAPx1_ASAP7_75t_R"
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set ::env(RE_BUFFER_CELL) ""
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set ::env(CELL_PAD) 2
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set ::env(CELL_PAD_EXCLUDE) ""
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# Clk Buffers info CTS data
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set ::env(ROOT_CLK_BUFFER) BUFx4_ASAP7_75t_R
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set ::env(CLK_BUFFER) BUFx4_ASAP7_75t_R
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set ::env(CLK_BUFFER_INPUT) A
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set ::env(CLK_BUFFER_OUTPUT) Y
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set ::env(CTS_CLK_BUFFER_LIST) "BUFx4_ASAP7_75t_R"
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set ::env(FP_PDN_RAIL_WIDTH) 0.48
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# Determined from BUFx24_ASAP7_75t_R
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set ::env(CTS_MAX_CAP) 1474.56
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set ::env(DEFAULT_MAX_TRAN) 320
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set ::env(PDN_CFG) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/grid_strategy-M2-M5-M7.cfg"

‎flow/platforms/asap7/openlane/asap7sc7p5t/no_synth.cells‎

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A2O1A1Ixp33_ASAP7_75t_R
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A2O1A1O1Ixp25_ASAP7_75t_R
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AO21x1_ASAP7_75t_R
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AO221x1_ASAP7_75t_R
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AO22x1_ASAP7_75t_R
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AO32x1_ASAP7_75t_R
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AO331x1_ASAP7_75t_R
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AO332x1_ASAP7_75t_R
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AO333x1_ASAP7_75t_R
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AOI211x1_ASAP7_75t_R
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AOI211xp5_ASAP7_75t_R
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AOI21x1_ASAP7_75t_R
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AOI21xp33_ASAP7_75t_R
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AOI21xp5_ASAP7_75t_R
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AOI221x1_ASAP7_75t_R
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AOI221xp5_ASAP7_75t_R
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AOI222xp33_ASAP7_75t_R
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AOI22x1_ASAP7_75t_R
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AOI22xp33_ASAP7_75t_R
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AOI22xp5_ASAP7_75t_R
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AOI311xp33_ASAP7_75t_R
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AOI31xp33_ASAP7_75t_R
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AOI31xp67_ASAP7_75t_R
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AOI321xp33_ASAP7_75t_R
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AOI322xp5_ASAP7_75t_R
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AOI32xp33_ASAP7_75t_R
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AOI331xp33_ASAP7_75t_R
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AOI332xp33_ASAP7_75t_R
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AOI333xp33_ASAP7_75t_R
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AOI33xp33_ASAP7_75t_R
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HB1xp67_ASAP7_75t_R
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HB2xp67_ASAP7_75t_R
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HB3xp67_ASAP7_75t_R
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HB4xp67_ASAP7_75t_R
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INVx1_ASAP7_75t_R
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INVxp33_ASAP7_75t_R
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INVxp67_ASAP7_75t_R
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O2A1O1Ixp33_ASAP7_75t_R
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O2A1O1Ixp5_ASAP7_75t_R
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OA331x1_ASAP7_75t_R
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OA332x1_ASAP7_75t_R
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OA333x1_ASAP7_75t_R
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OAI211xp5_ASAP7_75t_R
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OAI21x1_ASAP7_75t_R
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OAI21xp33_ASAP7_75t_R
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OAI21xp5_ASAP7_75t_R
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OAI221xp5_ASAP7_75t_R
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OAI222xp33_ASAP7_75t_R
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OAI22x1_ASAP7_75t_R
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OAI22xp33_ASAP7_75t_R
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OAI22xp5_ASAP7_75t_R
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OAI311xp33_ASAP7_75t_R
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OAI31xp33_ASAP7_75t_R
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OAI31xp67_ASAP7_75t_R
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OAI321xp33_ASAP7_75t_R
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OAI322xp33_ASAP7_75t_R
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OAI32xp33_ASAP7_75t_R
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OAI331xp33_ASAP7_75t_R
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OAI332xp33_ASAP7_75t_R
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OAI333xp33_ASAP7_75t_R
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OAI33xp33_ASAP7_75t_R
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ASYNC_DFFHx1_ASAP7_75t_R
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DFFHQNx1_ASAP7_75t_R
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DFFHQNx2_ASAP7_75t_R
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DFFHQNx3_ASAP7_75t_R
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DFFHQx4_ASAP7_75t_R
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DFFLQNx1_ASAP7_75t_R
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DHLx1_ASAP7_75t_R
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DLLx1_ASAP7_75t_R
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ICGx1_ASAP7_75t_R
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ICGx2_ASAP7_75t_R
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ICGx2p67DC_ASAP7_75t_R
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ICGx3_ASAP7_75t_R
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ICGx4DC_ASAP7_75t_R
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ICGx4_ASAP7_75t_R
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ICGx5_ASAP7_75t_R
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ICGx5p33DC_ASAP7_75t_R
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ICGx6p67DC_ASAP7_75t_R
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ICGx8DC_ASAP7_75t_R
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SDFHx1_ASAP7_75t_R
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SDFHx2_ASAP7_75t_R
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SDFHx3_ASAP7_75t_R
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SDFHx4_ASAP7_75t_R
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SDFLx1_ASAP7_75t_R
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SDFLx2_ASAP7_75t_R
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SDFLx3_ASAP7_75t_R
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SDFLx4_ASAP7_75t_R
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AND3x1_ASAP7_75t_R
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AND4x1_ASAP7_75t_R
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AND5x1_ASAP7_75t_R
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FAx1_ASAP7_75t_R
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HAxp5_ASAP7_75t_R
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MAJIxp5_ASAP7_75t_R
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NAND2x1_ASAP7_75t_R
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NAND2x1p5_ASAP7_75t_R
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NAND2xp33_ASAP7_75t_R
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NAND2xp5_ASAP7_75t_R
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NAND2xp67_ASAP7_75t_R
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NAND3x1_ASAP7_75t_R
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NAND3xp33_ASAP7_75t_R
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NAND4xp25_ASAP7_75t_R
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NAND4xp75_ASAP7_75t_R
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NAND5xp2_ASAP7_75t_R
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NOR2x1_ASAP7_75t_R
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NOR2x1p5_ASAP7_75t_R
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NOR2xp33_ASAP7_75t_R
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NOR2xp67_ASAP7_75t_R
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NOR3x1_ASAP7_75t_R
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NOR3xp33_ASAP7_75t_R
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NOR4xp25_ASAP7_75t_R
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NOR4xp75_ASAP7_75t_R
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NOR5xp2_ASAP7_75t_R
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OR3x1_ASAP7_75t_R
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OR4x1_ASAP7_75t_R
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OR5x1_ASAP7_75t_R
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TIEHIx1_ASAP7_75t_R
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TIELOx1_ASAP7_75t_R
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XNOR2x1_ASAP7_75t_R
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XNOR2xp5_ASAP7_75t_R
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XOR2x1_ASAP7_75t_R
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XOR2xp5_ASAP7_75t_R

‎flow/platforms/asap7/openlane/config.tcl‎

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# Process node
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set ::env(PROCESS) 7
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set ::env(DEF_UNITS_PER_MICRON) 1000
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# Placement site for core cells
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# This can be found in the technology lef
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set ::env(VDD_PIN) "VDD"
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set ::env(GND_PIN) "VSS"
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set ::env(STD_CELL_POWER_PINS) "VDD"
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set ::env(STD_CELL_GROUND_PINS) "VSS"
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# Technology LEF
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set ::env(TECH_LEF) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/techlef/asap7_tech_1x_201209.lef"
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set ::env(CELLS_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/lef/*.lef"]
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set ::env(GDS_FILES) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/gds/*.gds"]
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set ::env(STD_CELL_LIBRARY_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY)/cdl/$::env(STD_CELL_LIBRARY).cdl"
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set ::env(GPIO_PADS_LEF) ""
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set ::env(GPIO_PADS_VERILOG) ""
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# Optimization library
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set ::env(TECH_LEF_OPT) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/techlef/$::env(STD_CELL_LIBRARY_OPT).tlef"
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set ::env(CELLS_LEF_OPT) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/lef/*.lef"]
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set ::env(GDS_FILES_OPT) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/gds/*.gds"]
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set ::env(STD_CELL_LIBRARY_OPT_CDL) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/$::env(STD_CELL_LIBRARY_OPT)/cdl/$::env(STD_CELL_LIBRARY_OPT).cdl"
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# Optimization library slowest corner
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set tmp $::env(STD_CELL_LIBRARY)
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set ::env(STD_CELL_LIBRARY) $::env(STD_CELL_LIBRARY_OPT)
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source "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY_OPT)/config.tcl"
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set ::env(LIB_SLOWEST_OPT) $::env(LIB_SLOWEST)
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set ::env(STD_CELL_LIBRARY) $tmp
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source "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/config.tcl"
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set ::env(GPIO_PADS_LEF_CORE_SIDE) ""
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# magic setup
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#set ::env(MAGIC_MAGICRC) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/magic/sky130A.magicrc"
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#set ::env(MAGIC_TECH_FILE) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/magic/sky130A.tech"
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set ::env(RUN_MAGIC) false
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set ::env(RUN_KLAYOUT_XOR) false ;# nothing to XOR with from magic
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# Klayout setup
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set ::env(KLAYOUT_TECH) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/$::env(PDK).lyt"
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set ::env(KLAYOUT_PROPERTIES) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/$::env(PDK).lyp"
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#set ::env(KLAYOUT_DRC_TECH_SCRIPT) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/$::env(PDK)_mr.drc"
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#set ::env(KLAYOUT_DRC_TECH) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/klayout/$::env(PDK).lydrc"
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# netgen setup
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#set ::env(NETGEN_SETUP_FILE) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/netgen/sky130A_setup.tcl"
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set ::env(FP_TAPCELL_DIST) 25
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# Tracks info - suppress .info conversion and use make_tracks.tcl directly
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set ::env(TRACKS_INFO_FILE) ""
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set ::env(TRACKS_INFO_FILE_PROCESSED) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/make_tracks.tcl"
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# Latch mapping
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set ::env(SYNTH_LATCH_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/cells_latch.v"
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# Tri-state buffer mapping
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set ::env(TRISTATE_BUFFER_MAP) ""
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# Full adder mapping
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set ::env(FULL_ADDER_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/cells_adders.v"
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# Ripple carry adder mapping
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set ::env(RIPPLE_CARRY_ADDER_MAP) ""
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# Carry select adder mapping
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set ::env(CARRY_SELECT_ADDER_MAP) ""
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# Default No Synth List
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set ::env(NO_SYNTH_CELL_LIST) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/no_synth.cells"
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# Default DRC Exclude List
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set ::env(DRC_EXCLUDE_CELL_LIST) ""
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# DRC Exclude List for Optimization library
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set ::env(DRC_EXCLUDE_CELL_LIST_OPT) ""
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# Open-RCX Rules File
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set ::env(RCX_RULES) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/rcx_patterns.rules"
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# VIAS RC Values
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set ::env(VIAS_RC) "\
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V1 1.00E-02,\
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V2 1.00E-02,\
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V3 1.00E-02,\
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V4 1.00E-02,\
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V5 1.00E-02,\
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V6 1.00E-02,\
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V7 1.00E-02,\
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V8 1.00E-02,\
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V9 1.00E-02"
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# Layer RC Values
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set ::env(LAYERS_RC) "\
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M1 1.1368e-01 1.3889e-01,\
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M2 1.3426e-01 2.4222e-02,\
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M3 1.2918e-01 2.4222e-02,\
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M4 1.1396e-01 1.6778e-02,\
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M5 1.3323e-01 1.4677e-02,\
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M6 1.1575e-01 1.0371e-02,\
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M7 1.3293e-01 9.6720e-03,\
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M8 1.1822e-01 7.4310e-03,\
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M9 1.3497e-01 6.8740e-03"
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# Extra PDN configs
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set ::env(FP_PDN_RAILS_LAYER) met1
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set ::env(FP_PDN_LOWER_LAYER) met4
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set ::env(FP_PDN_UPPER_LAYER) met5
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set ::env(FP_PDN_RAIL_OFFSET) 0
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set ::env(FP_PDN_VWIDTH) 1.6
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set ::env(FP_PDN_HWIDTH) 1.6
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set ::env(FP_PDN_VSPACING) 1.7
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set ::env(FP_PDN_HSPACING) 1.7
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# Core Ring PDN defaults
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set ::env(FP_PDN_CORE_RING_VWIDTH) 1.6
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set ::env(FP_PDN_CORE_RING_HWIDTH) 1.6
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set ::env(FP_PDN_CORE_RING_VSPACING) 1.7
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set ::env(FP_PDN_CORE_RING_HSPACING) 1.7
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set ::env(FP_PDN_CORE_RING_VOFFSET) 6
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set ::env(FP_PDN_CORE_RING_HOFFSET) 6
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# PDN Macro blockages list
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set ::env(MACRO_BLOCKAGES_LAYER) "li1 met1 met2 met3 met4"
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# Used for parasitics estimation, IR drop analysis, etc
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set ::env(WIRE_RC_LAYER) "M3"
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set ::env(DATA_WIRE_RC_LAYER) "M3"
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set ::env(CLOCK_WIRE_RC_LAYER) "M3"
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# I/O Layer info
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set ::env(FP_IO_HLAYER) "M4"
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set ::env(FP_IO_VLAYER) "M5"
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# Routing Layer Info
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set ::env(GLB_RT_LAYER_ADJUSTMENTS) "0.5,0.5,0.5,0.5,0.5,0.5"
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set ::env(RT_MIN_LAYER) "M2"
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set ::env(RT_MAX_LAYER) "M7"
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# Use OR default
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set ::env(FP_IO_MIN_DISTANCE) ""
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# Asap7 has no antenna rules nor diode cells
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set ::env(DIODE_INSERTION_STRATEGY) 0

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