Modify user options for addition flexibility (#1142)

* Modify - to allow user control over additional attributes
         MOCK_ARRAY_ELEMENT_SIZE (width height)
         MOCK_ARRAY_ELEMENT_PITCH (x y)
         MOCK_ARRAY_TABLE (rows cols)

Signed-off-by: louiic <[email protected]>

* Modify - change usage of MOCK_ARRAY_TABLE

Signed-off-by: louiic <[email protected]>

* Modify example to conform to MOCK_ARRAY_TABL usage

Signed-off-by: louiic <[email protected]>

* Modify - pgrid_? to placement_grid_?

Signed-off-by: louiic <[email protected]>

* Modify - usage of MOCK_ARRAY_TABLE and subsequent call

Signed-off-by: louiic <[email protected]>

* Modify - usage of MOCK_ARRAY_TABLE
         now it includs row, cols, width, height, pitch_x and pitch_y

Signed-off-by: louiic <[email protected]>

* Modify - change user configurable variable to MOCK_ARRAY_TABLE
         to include rows, cols, width, height, pitch_x and pitch_y

Signed-off-by: louiic <[email protected]>

* Modify - change pgrid_? to placment_grid_?

Signed-off-by: louiic <[email protected]>

* To resolve merge issue.

Signed-off-by: louiic <[email protected]>

* Update OK

Signed-off-by: louiic <[email protected]>

---------

Signed-off-by: louiic <[email protected]>
Signed-off-by: Louii Chaiyakul <[email protected]>
Co-authored-by: louiic <[email protected]>
Co-authored-by: Louii Chaiyakul <[email protected]>

Author: openroad-robot

flow/designs/asap7/mock-array/Element/config.mk

@@ -1,10 +1,10 @@
 include designs/asap7/mock-array/defaults.mk
 
-export DESIGN_NAME = Element
-export DESIGN_NICKNAME = mock-array_Element
+export DESIGN_NAME            = Element
+export DESIGN_NICKNAME        = mock-array_Element
 
-export VERILOG_FILES = designs/src/mock-array/*.v
-export SDC_FILE      = designs/asap7/mock-array/Element/constraints.sdc
+export VERILOG_FILES          = designs/src/mock-array/*.v
+export SDC_FILE               = designs/asap7/mock-array/Element/constraints.sdc
 
 export PLATFORM               = asap7
 
@@ -13,30 +13,27 @@ export GPL_TIMING_DRIVEN      = 0
 export GPL_ROUTABILITY_DRIVEN = 0
 
 export CORE_AREA = $(shell \
- export MOCK_ARRAY_HEIGHT=$(MOCK_ARRAY_HEIGHT) && \
- export MOCK_ARRAY_WIDTH=$(MOCK_ARRAY_WIDTH) && \
- export MOCK_ARRAY_PITCH_SCALE=$(MOCK_ARRAY_PITCH_SCALE) && \
- cd designs/asap7/mock-array && \
- python3 -c "import config; print(f'{config.ce_margin_x} {config.ce_margin_y} {config.ce_width - config.ce_margin_x} {config.ce_height - config.ce_margin_y}')")
+  export MOCK_ARRAY_TABLE="$(MOCK_ARRAY_TABLE)" && \
+  cd $(dir $(DESIGN_CONFIG))/../ && \
+  python3 -c "import config; print(f'{config.ce_margin_x} {config.ce_margin_y} {config.ce_width - config.ce_margin_x} {config.ce_height - config.ce_margin_y}')")
+
 export DIE_AREA = $(shell \
- export MOCK_ARRAY_HEIGHT=$(MOCK_ARRAY_HEIGHT) && \
- export MOCK_ARRAY_WIDTH=$(MOCK_ARRAY_WIDTH) && \
- export MOCK_ARRAY_PITCH_SCALE=$(MOCK_ARRAY_PITCH_SCALE) && \
- cd designs/asap7/mock-array && \
- python3 -c "import config; print(f'0 0 {config.ce_width} {config.ce_height}')")
+  export MOCK_ARRAY_TABLE="$(MOCK_ARRAY_TABLE)" && \
+  cd $(dir $(DESIGN_CONFIG))/../ && \
+  python3 -c "import config; print(f'0 0 {config.ce_width} {config.ce_height}')")
 
-export IO_CONSTRAINTS = designs/asap7/mock-array/Element/io.tcl
+export IO_CONSTRAINTS         = designs/asap7/mock-array/Element/io.tcl
 
-export PDN_TCL = designs/asap7/mock-array/Element/pdn.tcl
+export PDN_TCL                = designs/asap7/mock-array/Element/pdn.tcl
 
-# max routing layer need to be set to M5, since M6 is needed for next level up to connect
-# to the ring and stipe
-#
 # If this design isn't quickly done in detailed routing, something is wrong.
 # At time of adding this option, only 3 iterations were needed for 0
 # violations.
 export DETAILED_ROUTE_ARGS=-bottom_routing_layer M2 -top_routing_layer M5 -save_guide_updates -verbose 1 -droute_end_iter 10
 
+export MOCK_ARRAY_ROWS        = $(word 1, $(MOCK_ARRAY_TABLE))
+export MOCK_ARRAY_COLS        = $(word 2, $(MOCK_ARRAY_TABLE))
+
 # since we are specifying DETAILED_ROUTE_ARGS, we need to communicate the
 # same information to other stages in the flow.
 export MIN_ROUTING_LAYER = M2

flow/designs/asap7/mock-array/Element/constraints.sdc

@@ -1,6 +1,6 @@
 set sdc_version 2.0
 
-set cols [expr {[info exists ::env(MOCK_ARRAY_WIDTH)] ? $::env(MOCK_ARRAY_WIDTH) : 8}]
+set cols [expr {[info exists ::env(MOCK_ARRAY_COLS)] ? $::env(MOCK_ARRAY_COLS) : 8}]
 
 set clk_name clock
 set clk_port_name clock

flow/designs/asap7/mock-array/README.md

@@ -4,20 +4,22 @@ Mock array big
 A mock array that can be configured in different sizes to generate
 interesting test-cases.
 
-By default, the array is 8x8 elements and has an 8 bit datapath.
+By default, the array is 8x8 elements, has an 8 bit datapath with 
+Element size of 4x4 unit and Element placement pitch of 6,6 - x,y direction.
 
-To create a 4x4 element array with 4 bit datapath, first create a settings.mk file:
+export MOCK_ARRAY_TABLE         ?= 8 8 4 4 6 6
+
+# Element'd data width
+export MOCK_ARRAY_DATAWIDTH     ?= 8
+
+To create a 4x4 element array with 4 bit datapath with element size of 5x6 and
+placement pitch of 8x6, set the user control variable MOCK_ARRAY_TABLE
 
 ```
-export MOCK_ARRAY_WIDTH=4
-export MOCK_ARRAY_HEIGHT=4
+export MOCK_ARRAY_TABLE="4 4 5 6 8 6"
 export MOCK_ARRAY_DATAWIDTH=4
 export FLOW_VARIANT=small
-# use a different folder for each combination of parameters
-#export MOCK_ARRAY_WIDTH=16
-#export MOCK_ARRAY_HEIGHT=16
-#export MOCK_ARRAY_DATAWIDTH=64
-#export FLOW_VARIANT=giant
+
 export DESIGN_CONFIG=designs/asap7/mock-array/config.mk
 ```
 

flow/designs/asap7/mock-array/config.mk

@@ -1,50 +1,49 @@
 include designs/asap7/mock-array/defaults.mk
 
-export DESIGN_NAME = MockArray
-export DESIGN_NICKNAME = mock-array
+export DESIGN_NAME            = MockArray
+export DESIGN_NICKNAME        = mock-array
 
 export VERILOG_FILES_BLACKBOX = designs/src/mock-array/Element.v
-export VERILOG_FILES = designs/src/mock-array/*.v
+export VERILOG_FILES          = designs/src/mock-array/*.v
 
-export SDC_FILE      = designs/asap7/mock-array/constraints.sdc
+export SDC_FILE               = designs/asap7/mock-array/constraints.sdc
 
 export PLATFORM               = asap7
 
 export PLACE_DENSITY          = 0.30
 
 export CORE_AREA = $(shell \
- export MOCK_ARRAY_HEIGHT=$(MOCK_ARRAY_HEIGHT) && \
- export MOCK_ARRAY_WIDTH=$(MOCK_ARRAY_WIDTH) && \
- export MOCK_ARRAY_PITCH_SCALE=$(MOCK_ARRAY_PITCH_SCALE) && \
- cd designs/asap7/mock-array && \
- python3 -c "import config; print(f'{config.margin_x} {config.margin_y} {config.core_width + config.margin_x} {config.core_height + config.margin_y}')")
-export DIE_AREA = $(shell \
- export MOCK_ARRAY_HEIGHT=$(MOCK_ARRAY_HEIGHT) && \
- export MOCK_ARRAY_WIDTH=$(MOCK_ARRAY_WIDTH) && \
- export MOCK_ARRAY_PITCH_SCALE=$(MOCK_ARRAY_PITCH_SCALE) && \
- cd designs/asap7/mock-array && \
- python3 -c "import config; print(f'0 0 {config.die_width} {config.die_height}')")
+  export MOCK_ARRAY_TABLE="$(MOCK_ARRAY_TABLE)"  && \
+  cd $(dir $(DESIGN_CONFIG)) && \
+  python3 -c "import config ; print(f'{config.margin_x} {config.margin_y} {config.core_width + config.margin_x} {config.core_height + config.margin_y}')")
 
-BLOCKS = Element
+export DIE_AREA  = $(shell \
+  export MOCK_ARRAY_TABLE="$(MOCK_ARRAY_TABLE)" && \
+  cd $(dir $(DESIGN_CONFIG)) && \
+  python3 -c "import config; print(f'{0} {0} {config.die_width} {config.die_height}')")
 
-export GDS_ALLOW_EMPTY = Element
+BLOCKS                       = Element
 
-export MACRO_PLACEMENT_TCL = ./designs/asap7/mock-array/macro-placement.tcl
+export GDS_ALLOW_EMPTY       = Element
 
-export IO_CONSTRAINTS = designs/asap7/mock-array/io.tcl
+export MACRO_PLACEMENT_TCL   = ./designs/asap7/mock-array/macro-placement.tcl
+
+export IO_CONSTRAINTS        = designs/asap7/mock-array/io.tcl
+
+export PDN_TCL               = designs/asap7/mock-array/pdn.tcl
 
-export PDN_TCL = designs/asap7/mock-array/pdn.tcl
 export TNS_END_PERCENT       = 100
 
-# Target to force generation of Verilog per user settings
-#   MOCK_ARRAY_WIDTH and MOCK_ARRAY_HEIGHT
+# Target to force generation of Verilog per user settings MOCK_ARRAY_TABLE (rows, cols)
 verilog:
+	export MOCK_ARRAY_ROWS=$(word 1, $(MOCK_ARRAY_TABLE)) ; \
+	export MOCK_ARRAY_COLS=$(word 2, $(MOCK_ARRAY_TABLE)) ; \
 	./designs/asap7/mock-array/verilog.sh
 
 # If this design isn't quickly done in detailed routing, something is wrong.
 # At time of adding this option, only 12 iterations were needed for 0
 # violations.
-export DETAILED_ROUTE_ARGS=-bottom_routing_layer M2 -top_routing_layer M7 -save_guide_updates -verbose 1 -droute_end_iter 15
+export DETAILED_ROUTE_ARGS   = -bottom_routing_layer M2 -top_routing_layer M7 -save_guide_updates -verbose 1 -droute_end_iter 15
 
 # since we are specifying DETAILED_ROUTE_ARGS, we need to communicate the
 # same information to other stages in the flow.

flow/designs/asap7/mock-array/config.py

@@ -1,47 +1,34 @@
 import os
 
-# number of Elements in row and column, user can set via environment variable
-rows = int(os.environ.get("MOCK_ARRAY_HEIGHT"))
-cols = int(os.environ.get("MOCK_ARRAY_WIDTH"))
-
-# Element placement pitch can be control by user
-pitch_scale = int(os.environ.get("MOCK_ARRAY_PITCH_SCALE"))
-
-if pitch_scale < 1:
-  raise Exception("Element placement pitch must be greater than 1")
-
-# Routing pitches for relevant metal layers.
-#  For x, this is M5; for y, this is M4.
-#  Pitches are specified in OpenROAD-flow-scripts/flow/platforms/asap7/lef/asap7_tech_1x_201209.lef.
-#  For asap7, x and y pitch is the same.
-#
-# make_tracks M5 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.012 -y_pitch 0.048
-#
-# the macro needs to be on a multiple of the track pattern
-routing_pitch = 0.048
-
-placement_grid_x = routing_pitch
-placement_grid_y = routing_pitch
-
-# historically pitch_scale 2 was ca 13 um
-ce_width    = int(3 * 2.16 / placement_grid_x) * placement_grid_x * pitch_scale
-ce_height   = int(3 * 2.16 / placement_grid_y) * placement_grid_y * pitch_scale
-ce_margin_x = placement_grid_x * 8
-ce_margin_y = placement_grid_y * 8
+# routing pitch for M4, M5 and M6 tied to placement grid at 2.16
+# therefore, the optimal placement and Element size should be multiple of 2.16
+# set grid x and y
+placement_grid_x     = 2.16
+placement_grid_y     = 2.16
+
+# number of Elements in row and column, can be control by user via environment variable 
+# MOCK_ARRAY_TABLE (rows, cols, width, height, pitch_x, pitch_y)
+#  rows, cols       - number of Element in rows, cols
+#  width, height    - width and height of each Element
+#  pitch_x, pitch_y - placement pitch for each Element, in x and y direction
+# specification are in unit of placement grid
+rows, cols, ce_x, ce_y, pitch_x, pitch_y = map(int, os.environ.get("MOCK_ARRAY_TABLE").split())
+
+# Element size is set to multiple of placement grid above
+ce_width    = ce_x * placement_grid_x
+ce_height   = ce_y * placement_grid_y
 
 # top level core offset 
-margin_x    = int(2.16 / placement_grid_x) * placement_grid_x
-margin_y    = int(2.16 / placement_grid_y) * placement_grid_y
-
-channel = 12 # int(os.environ.get("MACRO_PLACE_CHANNEL").split()[0])
+margin_x    = placement_grid_x
+margin_y    = placement_grid_y
 
-# Element placement, can be controlled by user
-ce_pitch_x  = ce_width + int((channel * 2) / placement_grid_x) * placement_grid_x
-ce_pitch_y  = ce_height + int((channel * 2) / placement_grid_y) * placement_grid_y
+# Element core margin
+ce_margin_x = placement_grid_x * 0.5
+ce_margin_y = placement_grid_y * 0.5
 
-# top level core size
-core_width  = ce_pitch_x * cols + ce_width
-core_height = ce_pitch_y * rows + ce_height
+# top level core and die size
+core_width  = ((placement_grid_x * pitch_x) * (cols + 1)) + (ce_width  * cols)
+core_height = ((placement_grid_y * pitch_y) * (rows + 1)) + (ce_height * rows)
 
-die_width = core_width + (2 * margin_x)
-die_height = core_height + (2 * margin_y)
+die_width  = core_width  + (margin_x * 2)
+die_height = core_height + (margin_y * 2)

flow/designs/asap7/mock-array/defaults.mk

@@ -1,5 +1,10 @@
 # single source of truth for defaults.
-export MOCK_ARRAY_WIDTH ?= 8
-export MOCK_ARRAY_HEIGHT ?= 8
-export MOCK_ARRAY_DATAWIDTH ?= 8
-export MOCK_ARRAY_PITCH_SCALE ?= 2
+# each number is a unit
+# current unit is configured as 2.16 which is on the routing grid for M5
+
+# table of Elements - (rows cols width height pitch_x pitch_y)
+export MOCK_ARRAY_TABLE         ?= 8 8 4 4 6 6
+
+# Element'd data width
+export MOCK_ARRAY_DATAWIDTH     ?= 8
+

flow/designs/asap7/mock-array/macro-placement.tcl

@@ -1,16 +1,20 @@
 # fish out values from single source of truth: config.py
-set vals [regexp -all -inline {\S+} [exec sh -c {cd designs/asap7/mock-array && python3 -c "import config;print(f'{config.rows} {config.cols} {config.ce_pitch_x} {config.ce_pitch_y} {config.margin_x} {config.margin_y} {config.placement_grid_x} {config.placement_grid_y}')"}]]
-lassign $vals rows cols ce_pitch_x ce_pitch_y margin_x margin_y placement_grid_x placement_grid_y
+set vals [regexp -all -inline {\S+} [exec sh -c {cd designs/asap7/mock-array && python3 -c "import config;print(f'{config.rows} {config.cols} {config.pitch_x} {config.pitch_y} {config.margin_x} {config.margin_y} {config.placement_grid_x} {config.placement_grid_y}')"}]]
+lassign $vals rows cols pitch_x pitch_y margin_x margin_y placement_grid_x placement_grid_y
 
 set block [ord::get_db_block]
 set units [$block getDefUnits]
 
 for {set row 0} {$row < $rows} {incr row} {
   for {set col 0} {$col < $cols} {incr col} {
     set inst [$block findInst [format "ces_%d_%d" $row $col]]
+    set bbox [$inst getBBox]
 
-    set x [expr int(int(($margin_x + ($ce_pitch_x / 2) + ($ce_pitch_x * $col)) / $placement_grid_x) * $placement_grid_x * $units)]
-    set y [expr int(int(($margin_y + ($ce_pitch_y / 2) + ($ce_pitch_y * $row)) / $placement_grid_y) * $placement_grid_y * $units)]
+    set w [$bbox getDX]
+    set h [$bbox getDY]
+
+    set x [expr int((($margin_x + (($placement_grid_x * $pitch_x) * ($col + 1.0))) * $units) + ($w * $col))]
+    set y [expr int((($margin_y + (($placement_grid_y * $pitch_y) * ($row + 1.0))) * $units) + ($h * $row))]
 
     $inst setOrient R0
     $inst setOrigin $x $y