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2 parents 1cbb914 + 73c4fd1 commit b71aee2Copy full SHA for b71aee2
flow/designs/asap7/swerv_wrapper/config.mk
@@ -9,6 +9,8 @@ export RTLMP_MIN_INST = 5000
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export RTLMP_MAX_MACRO = 30
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export RTLMP_MIN_MACRO = 4
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+export LIB_MODEL = CCS
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+
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export VERILOG_FILES = ./designs/src/swerv/swerv_wrapper.sv2v.v \
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./designs/$(PLATFORM)/swerv_wrapper/macros.v
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export SDC_FILE = ./designs/$(PLATFORM)/swerv_wrapper/constraint.sdc
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