Merge remote-tracking branch 'private/master' into secure-grt-rudy-tweak

Author: gudeh

flow/Makefile

@@ -100,6 +100,7 @@
 #DESIGN_CONFIG=./designs/ihp-sg13g2/gcd/config.mk
 #DESIGN_CONFIG=./designs/ihp-sg13g2/spi/config.mk
 #DESIGN_CONFIG=./designs/ihp-sg13g2/riscv32i/config.mk
+#DESIGN_CONFIG=./designs/ihp-sg13g2/i2c-gpio-expander/config.mk
 
 # Default design
 DESIGN_CONFIG ?= ./designs/nangate45/gcd/config.mk
@@ -178,9 +179,6 @@ include $(PLATFORM_DIR)/config.mk
 # is no way to escape space in defaults.py and get "foreach" to work.
 $(foreach line,$(shell $(SCRIPTS_DIR)/defaults.py),$(eval export $(subst __SPACE__, ,$(line))))
 
-# Enables hierarchical yosys
-export SYNTH_STATS = $(RESULTS_DIR)/synth_stats.txt
-export SYNTH_STATS_SCRIPT = $(SCRIPTS_DIR)/synth_stats.tcl
 # If the design, nor $(PLATFORM_DIR)/config.mk provided a default, provide one here
 export MAX_UNGROUP_SIZE ?= 0
 
@@ -454,13 +452,6 @@ memory:
 
 export SYNTH_SCRIPT ?= $(SCRIPTS_DIR)/synth.tcl
 export SYNTH_MEMORY_MAX_BITS ?= 4096
-
-.PHONY: do-yosys-stats
-do-yosys-stats:
-	mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR)
-	(export VERILOG_FILES=$(RESULTS_DIR)/1_synth.rtlil; \
-	$(TIME_CMD) $(YOSYS_EXE) $(YOSYS_FLAGS) -c $(SYNTH_STATS_SCRIPT)) 2>&1 | tee $(abspath $(LOG_DIR)/1_1_yosys_stats.log)
-
 export SDC_FILE_CLOCK_PERIOD = $(RESULTS_DIR)/clock_period.txt
 
 $(SDC_FILE_CLOCK_PERIOD): $(SDC_FILE)
@@ -487,7 +478,7 @@ $(RESULTS_DIR)/1_synth.rtlil: $(YOSYS_DEPENDENCIES)
 	$(UNSET_AND_MAKE) do-yosys-canonicalize
 
 $(RESULTS_DIR)/1_1_yosys.v: $(RESULTS_DIR)/1_synth.rtlil
-	$(UNSET_AND_MAKE) do-yosys-stats do-yosys
+	$(UNSET_AND_MAKE) do-yosys
 
 .PHONY: do-synth
 do-synth:

flow/designs/asap7/aes-block/autotuner.json

@@ -3,16 +3,16 @@
     "_SDC_CLK_PERIOD": {
         "type": "float",
         "minmax": [
-            100,
+            300,
             600
         ],
         "step": 0
     },
     "CORE_UTILIZATION": {
         "type": "int",
         "minmax": [
-            0,
-            20
+            20,
+            50
         ],
         "step": 1
     },
@@ -35,16 +35,16 @@
     "CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": {
         "type": "int",
         "minmax": [
-            1,
-            5
+            0,
+            3
         ],
         "step": 1
     },
     "CELL_PAD_IN_SITES_DETAIL_PLACEMENT": {
         "type": "int",
         "minmax": [
-            1,
-            5
+            0,
+            3
         ],
         "step": 1
     },
@@ -60,7 +60,7 @@
         "type": "float",
         "minmax": [
             0.0,
-            0.99
+            0.2
         ],
         "step": 0
     },

flow/designs/asap7/aes-block/config.mk

@@ -8,8 +8,8 @@ export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.
 
 export ABC_AREA               = 1
 
-export CORE_UTILIZATION       = 20
-export CORE_ASPECT_RATIO      = 1
+export CORE_UTILIZATION       = 27
+export CORE_ASPECT_RATIO      = 0.867
 export CORE_MARGIN            = 2
 export PLACE_DENSITY          = 0.65
 
@@ -29,4 +29,11 @@ export PWR_NETS_VOLTAGES      =
 # The macros are very small so use a smaller halo
 export MACRO_PLACE_HALO        ?= 5 5
 
-export ROUTING_LAYER_ADJUSTMENT = 0.3
+export ROUTING_LAYER_ADJUSTMENT = 0.23
+
+# Parameters from AutoTuner runs
+export CELL_PAD_IN_SITES_GLOBAL_PLACEMENT = 2
+export CELL_PAD_IN_SITES_DETAIL_PLACEMENT = 1
+export CTS_CLUSTER_SIZE = 155
+export CTS_CLUSTER_DIAMETER = 248
+export PLACE_DENSITY_LB_ADDON = 0.14

flow/designs/asap7/aes-block/constraint.sdc

@@ -1,6 +1,6 @@
 set clk_name  clk
 set clk_port_name clk
-set clk_period 400 
+set clk_period 475
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]