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synth: Convert Ibex design to SV originals
Signed-off-by: Martin Povišer <[email protected]>
1 parent dd5e62e commit b95d6c7

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‎flow/designs/asap7/ibex/config.mk‎

Lines changed: 26 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,32 @@ export PLATFORM = asap7
33
export DESIGN_NICKNAME = ibex
44
export DESIGN_NAME = ibex_core
55

6-
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
6+
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pkg.sv \
7+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.sv \
8+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.sv \
9+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.sv \
10+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.sv \
11+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.sv \
12+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.sv \
13+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.sv \
14+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.sv \
15+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.sv \
16+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.sv \
17+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.sv \
18+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.sv \
19+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.sv \
20+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.sv \
21+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.sv \
22+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.sv \
23+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.sv \
24+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.sv \
25+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.sv \
26+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/syn/rtl/prim_clock_gating.v
27+
28+
export VERILOG_INCLUDE_DIRS = \
29+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/lowrisc_ip/prim/rtl/
30+
31+
export SYNTH_USE_SLANG = 1
732

833
# if FLOW_VARIANT == pos_slack, use an SDC file that has a larger clock
934
# resulting in positive slack

‎flow/designs/gf12/ibex/config.mk‎

Lines changed: 26 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -2,46 +2,32 @@ export DESIGN_NICKNAME = ibex
22
export DESIGN_NAME = ibex_core
33
export PLATFORM = gf12
44

5-
6-
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \
7-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \
8-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \
9-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \
10-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \
11-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \
12-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \
13-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \
14-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \
15-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \
16-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \
17-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \
18-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \
19-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \
20-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \
21-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \
22-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \
23-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \
24-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \
25-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \
26-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \
27-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \
28-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \
29-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \
30-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \
31-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \
32-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \
33-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \
34-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \
35-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \
36-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \
37-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \
38-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \
39-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \
40-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \
41-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \
42-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v
43-
44-
5+
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pkg.sv \
6+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.sv \
7+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.sv \
8+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.sv \
9+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.sv \
10+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.sv \
11+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.sv \
12+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.sv \
13+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.sv \
14+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.sv \
15+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.sv \
16+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.sv \
17+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.sv \
18+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.sv \
19+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.sv \
20+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.sv \
21+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.sv \
22+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.sv \
23+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.sv \
24+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.sv \
25+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/syn/rtl/prim_clock_gating.v
26+
27+
export VERILOG_INCLUDE_DIRS = \
28+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/lowrisc_ip/prim/rtl/
29+
30+
export SYNTH_USE_SLANG = 1
4531

4632
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
4733

‎flow/designs/gf180/ibex/config.mk‎

Lines changed: 26 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -2,43 +2,32 @@ export DESIGN_NICKNAME = ibex
22
export DESIGN_NAME = ibex_core
33
export PLATFORM = gf180
44

5-
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \
6-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \
7-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \
8-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \
9-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \
10-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \
11-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \
12-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \
13-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \
14-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \
15-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \
16-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \
17-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \
18-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \
19-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \
20-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \
21-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \
22-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \
23-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \
24-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \
25-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \
26-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \
27-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \
28-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \
29-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \
30-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \
31-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \
32-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \
33-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \
34-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \
35-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \
36-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \
37-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \
38-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \
39-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \
40-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \
41-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v
5+
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pkg.sv \
6+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.sv \
7+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.sv \
8+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.sv \
9+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.sv \
10+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.sv \
11+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.sv \
12+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.sv \
13+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.sv \
14+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.sv \
15+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.sv \
16+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.sv \
17+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.sv \
18+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.sv \
19+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.sv \
20+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.sv \
21+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.sv \
22+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.sv \
23+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.sv \
24+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.sv \
25+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/syn/rtl/prim_clock_gating.v
26+
27+
export VERILOG_INCLUDE_DIRS = \
28+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/lowrisc_ip/prim/rtl/
29+
30+
export SYNTH_USE_SLANG = 1
4231

4332
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
4433

‎flow/designs/ihp-sg13g2/ibex/config.mk‎

Lines changed: 26 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -2,43 +2,32 @@ export DESIGN_NICKNAME = ibex
22
export DESIGN_NAME = ibex_core
33
export PLATFORM = ihp-sg13g2
44

5-
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.v \
6-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_branch_predict.v \
7-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.v \
8-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.v \
9-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.v \
10-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.v \
11-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.v \
12-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.v \
13-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.v \
14-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_dummy_instr.v \
15-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.v \
16-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.v \
17-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_icache.v \
18-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.v \
19-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.v \
20-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.v \
21-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.v \
22-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.v \
23-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.v \
24-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.v \
25-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.v \
26-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_fpga.v \
27-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_latch.v \
28-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.v \
29-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_badbit_ram_1p.v \
30-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_clock_gating.v \
31-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_clock_gating.v \
32-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_generic_ram_1p.v \
33-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_lfsr.v \
34-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_ram_1p.v \
35-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_dec.v \
36-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_28_22_enc.v \
37-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_dec.v \
38-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_39_32_enc.v \
39-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_dec.v \
40-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_secded_72_64_enc.v \
41-
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/prim_xilinx_clock_gating.v
5+
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pkg.sv \
6+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.sv \
7+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.sv \
8+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.sv \
9+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.sv \
10+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.sv \
11+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.sv \
12+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.sv \
13+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.sv \
14+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.sv \
15+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.sv \
16+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.sv \
17+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.sv \
18+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.sv \
19+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.sv \
20+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.sv \
21+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.sv \
22+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.sv \
23+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.sv \
24+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.sv \
25+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/syn/rtl/prim_clock_gating.v
26+
27+
export VERILOG_INCLUDE_DIRS = \
28+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/lowrisc_ip/prim/rtl/
29+
30+
export SYNTH_USE_SLANG = 1
4231

4332
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
4433

‎flow/designs/intel16/ibex/config.mk‎

Lines changed: 27 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,33 @@ export DESIGN_NICKNAME = ibex
55
export DESIGN_NAME = ibex_core
66
export PLATFORM = intel16
77

8-
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
8+
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pkg.sv \
9+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_alu.sv \
10+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_compressed_decoder.sv \
11+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_controller.sv \
12+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_cs_registers.sv \
13+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_counter.sv \
14+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_decoder.sv \
15+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_ex_block.sv \
16+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_id_stage.sv \
17+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_if_stage.sv \
18+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_wb_stage.sv \
19+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_load_store_unit.sv \
20+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_slow.sv \
21+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_multdiv_fast.sv \
22+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_prefetch_buffer.sv \
23+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_fetch_fifo.sv \
24+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_pmp.sv \
25+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_csr.sv \
26+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_core.sv \
27+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/ibex_register_file_ff.sv \
28+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/syn/rtl/prim_clock_gating.v
29+
30+
export VERILOG_INCLUDE_DIRS = \
31+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/vendor/lowrisc_ip/prim/rtl/
32+
33+
export SYNTH_USE_SLANG = 1
34+
935
export SDC_FILE = $(DESIGN_DIR)/constraint.sdc
1036

1137
export CORE_UTILIZATION = 30

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