Merge pull request #3263 from Pinata-Consulting/variables-cleanup

variables: cleanup

Author: maliberty

flow/scripts/global_place.tcl

@@ -39,7 +39,7 @@ proc do_placement {global_placement_args} {
     -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT)] \
     $global_placement_args]
 
-  lappend all_args {*}$::env(GLOBAL_PLACEMENT_ARGS)
+  lappend all_args {*}[env_var_or_empty GLOBAL_PLACEMENT_ARGS]
 
   log_cmd global_placement {*}$all_args
 }

flow/scripts/global_place_skip_io.tcl

@@ -8,7 +8,7 @@ if { [env_var_exists_and_non_empty FLOORPLAN_DEF] } {
   log_cmd global_placement -skip_io -density [place_density_with_lb_addon] \
       -pad_left $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \
       -pad_right $::env(CELL_PAD_IN_SITES_GLOBAL_PLACEMENT) \
-      {*}$::env(GLOBAL_PLACEMENT_ARGS)
+      {*}[env_var_or_empty GLOBAL_PLACEMENT_ARGS]
 }
 
 write_db $::env(RESULTS_DIR)/3_1_place_gp_skip_io.odb

flow/scripts/io_placement.tcl

@@ -8,7 +8,7 @@ if {![env_var_exists_and_non_empty FLOORPLAN_DEF] && \
   log_cmd place_pins \
     -hor_layers $::env(IO_PLACER_H) \
     -ver_layers $::env(IO_PLACER_V) \
-    {*}$::env(PLACE_PINS_ARGS)
+    {*}[env_var_or_empty PLACE_PINS_ARGS]
   write_db $::env(RESULTS_DIR)/3_2_place_iop.odb
   write_pin_placement $::env(RESULTS_DIR)/3_2_place_iop.tcl
 } else {

flow/scripts/synth.tcl

@@ -21,7 +21,7 @@ if {[env_var_exists_and_non_empty SYNTH_HIER_SEPARATOR]} {
   scratchpad -set flatten.separator $::env(SYNTH_HIER_SEPARATOR)
 }
 
-set synth_full_args $::env(SYNTH_ARGS)
+set synth_full_args [env_var_or_empty SYNTH_ARGS]
 if {[env_var_exists_and_non_empty SYNTH_OPERATIONS_ARGS]} {
   set synth_full_args [concat $synth_full_args $::env(SYNTH_OPERATIONS_ARGS)]
 } else {

flow/scripts/synth_canonicalize.tcl

@@ -1,7 +1,7 @@
 source $::env(SCRIPTS_DIR)/synth_preamble.tcl
 read_design_sources
 
-dict for {key value} $::env(VERILOG_TOP_PARAMS) {
+dict for {key value} [env_var_or_empty VERILOG_TOP_PARAMS] {
   # Apply toplevel parameters
   chparam -set $key $value $::env(DESIGN_NAME)
 }

flow/scripts/synth_preamble.tcl

@@ -48,20 +48,22 @@ proc read_design_sources {} {
     plugin -i slang
     yosys read_slang -D SYNTHESIS --keep-hierarchy --compat=vcs \
       --ignore-assertions --top $::env(DESIGN_NAME) \
-      {*}$vIdirsArgs {*}$::env(VERILOG_FILES) {*}$::env(VERILOG_DEFINES)
+      {*}$vIdirsArgs {*}$::env(VERILOG_FILES) {*}[env_var_or_empty VERILOG_DEFINES]
     # Workaround for yosys-slang#119
     setattr -unset init
   } elseif {[env_var_equals SYNTH_HDL_FRONTEND verific]} {
     if {[env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS]} {
-	verific -vlog-incdir {*}$::env(VERILOG_INCLUDE_DIRS)
+	    verific -vlog-incdir {*}$::env(VERILOG_INCLUDE_DIRS)
     }
     if {[env_var_exists_and_non_empty VERILOG_DEFINES]} {
-	verific -vlog-define {*}$::env(VERILOG_DEFINES)
+	    verific -vlog-define {*}$::env(VERILOG_DEFINES)
     }
     verific -sv2012 {*}$::env(VERILOG_FILES)
   } elseif {![env_var_exists_and_non_empty SYNTH_HDL_FRONTEND]} {
     verilog_defaults -push
-    verilog_defaults -add {*}$::env(VERILOG_DEFINES)
+    if {[env_var_exists_and_non_empty VERILOG_DEFINES]} {
+      verilog_defaults -add {*}$::env(VERILOG_DEFINES)
+    }
     foreach file $::env(VERILOG_FILES) {
       read_verilog -defer -sv {*}$vIdirsArgs $file
     }

flow/scripts/util.tcl

@@ -124,6 +124,14 @@ proc append_env_var {list_name var_name prefix has_arg} {
   }
 }
 
+# Non-empty defaults should go into variables.yaml, generally
+proc env_var_or_empty {env_var} {
+  if {[env_var_exists_and_non_empty $env_var]} {
+    return $::env($env_var)
+  }
+  return ""
+}
+
 proc find_macros {} {
   set macros ""
 

flow/scripts/variables.yaml

@@ -377,7 +377,6 @@ PLACE_PINS_ARGS:
     Arguments to place_pins
   stages:
     - place
-  default: ""
 PLACE_DENSITY:
   description: >
     The desired average placement density of cells: 1.0 = dense, 0.0 = widely spread.
@@ -407,7 +406,6 @@ GLOBAL_PLACEMENT_ARGS:
   description: >
     Use additional tuning parameters during global placement other than default
     args defined in global_place.tcl.
-  default: ""
 ENABLE_DPO:
   description: |
     Enable detail placement with improve_placement feature.
@@ -603,7 +601,6 @@ VERILOG_DEFINES:
   description: >
     Preprocessor defines passed to the language frontend.
     Example: `-D HPDCACHE_ASSERT_OFF`
-  default: ""
   stages:
     - synth
 SDC_FILE:
@@ -683,7 +680,6 @@ SYNTH_KEEP_MODULES:
 SYNTH_ARGS:
   description: |
     Optional synthesis variables for yosys.
-  default: ""
 SYNTH_HIER_SEPARATOR:
   description: |
     Separator used for the synthesis flatten stage.
@@ -693,7 +689,6 @@ VERILOG_TOP_PARAMS:
     Apply toplevel params (if exist).
   stages:
     - synth
-  default: ""
 CORE_ASPECT_RATIO:
   description: >
     The core aspect ratio (height / width). This value is ignored if