11load ("@bazel-orfs//:openroad.bzl" , "orfs_flow" )
2+ load ("@rules_python//python:pip.bzl" , "compile_pip_requirements" )
23
34filegroup (
45 name = "constraints-gcd" ,
@@ -25,10 +26,9 @@ orfs_flow(
2526 stage_sources = {
2627 "synth" : [":constraints-gcd" ],
2728 },
28- verilog_files = glob (include = ["designs/src/gcd/*.v" ]),
29+ verilog_files = glob (include = ["designs/src/gcd/*.v" ]),
2930)
3031
31-
3232filegroup (
3333 name = "constraints-swerv" ,
3434 srcs = [
@@ -37,30 +37,26 @@ filegroup(
3737 visibility = [":__subpackages__" ],
3838)
3939
40- filegroup (
41- name = "swerv-fastroute" ,
42- srcs = [
43- "designs/asap7/swerv_wrapper/fastroute.tcl" ,
44- ],
45- visibility = [":__subpackages__" ],
46- )
47-
4840filegroup (
4941 name = "additional_lefs" ,
50- srcs = glob (include = ["designs/asap7/swerv_wrapper/lef/*.lef" ])
42+ srcs = glob (include = ["designs/asap7/swerv_wrapper/lef/*.lef" ]),
5143)
44+
5245filegroup (
5346 name = "additional_libs" ,
54- srcs = glob (include = ["designs/asap7/swerv_wrapper/lib/*.lib" ])
47+ srcs = glob (include = ["designs/asap7/swerv_wrapper/lib/*.lib" ]),
5548)
5649
5750SWERV_ALL = {
58- "LIB_MODEL" :"CCS" ,
51+ "LIB_MODEL" : "CCS" ,
5952 "ADDITIONAL_LEFS" : "$(locations :additional_lefs)" ,
6053 "ADDITIONAL_LIBS" : "$(locations :additional_libs)" ,
6154}
6255
63- all_sources = [":additional_lefs" , ":additional_libs" ]
56+ all_sources = [
57+ ":additional_lefs" ,
58+ ":additional_libs" ,
59+ ]
6460
6561orfs_flow (
6662 name = "swerv_wrapper" ,
@@ -76,7 +72,7 @@ orfs_flow(
7672 "RTLMP_MIN_MACRO" : "4" ,
7773 "DIE_AREA" : "0 0 550 600" ,
7874 "CORE_AREA" : "5 5 545 595" ,
79- "PLACE_PINS_ARGS" : "-exclude left:* -exclude right:*"
75+ "PLACE_PINS_ARGS" : "-exclude left:* -exclude right:*" ,
8076 },
8177 "place" : SWERV_ALL | {
8278 "PLACE_PINS_ARGS" : "-exclude left:* -exclude right:*" ,
@@ -85,29 +81,26 @@ orfs_flow(
8581 "cts" : SWERV_ALL | {
8682 "TNS_END_PERCENT" : "100" ,
8783 },
88- "route" : SWERV_ALL | {
89- "FASTROUTE_TCL" : "$(location :swerv-fastroute)" ,
90- },
84+ "route" : SWERV_ALL ,
9185 "final" : SWERV_ALL | {
9286 "PWR_NETS_VOLTAGEsS" : "" ,
9387 "GND_NETS_VOLTAGES" : "" ,
94- }
88+ },
9589 },
96- verilog_files = glob (include = [
97- "designs/src/swerv/swerv_wrapper.sv2v.v" ,
98- "designs/asap7/swerv_wrapper/macros.v"
99- ]),
10090 stage_sources = {
10191 "synth" : all_sources + [":constraints-swerv" ],
10292 "floorplan" : all_sources ,
10393 "place" : all_sources ,
10494 "cts" : all_sources ,
105- "route" : all_sources + [ ":swerv-fastroute" ] ,
95+ "route" : all_sources ,
10696 "final" : all_sources ,
10797 },
98+ verilog_files = glob (include = [
99+ "designs/src/swerv/swerv_wrapper.sv2v.v" ,
100+ "designs/asap7/swerv_wrapper/macros.v" ,
101+ ]),
108102)
109103
110-
111104filegroup (
112105 name = "mock-array-constraints" ,
113106 srcs = [
@@ -119,34 +112,26 @@ filegroup(
119112filegroup (
120113 name = "mock-array-io" ,
121114 srcs = [
122- "designs/asap7/mock-array/io.tcl"
115+ "designs/asap7/mock-array/io.tcl" ,
123116 ],
124117 data = [
125118 "designs/src/mock-array/util.tcl" ,
126119 ],
127120 visibility = [":__subpackages__" ],
128121)
129122
130- filegroup (
131- name = "mock-array-fastroute" ,
132- srcs = [
133- "designs/asap7/mock-array/fastroute.tcl" ,
134- ],
135- visibility = [":__subpackages__" ],
136- )
137-
138123MOCK_ARRAY_FLOORPLAN_PLACE = {
139124 "PLACE_PINS_ARGS" : "-annealing" ,
140125 "IO_CONSTRAINTS" : "$(location :mock-array-io)" ,
141126 "PLACE_DENSITY" : "0.30" ,
142- "DIE_AREA" : "0 0 358.56 388.8" ,
143- "CORE_AREA" : "2.16 2.16 356.40000000000003 386.64000000000004" ,
144- "MACRO_PLACE_HALO" : "0 2.16" ,
145- "RTLMP_BOUNDARY_WT" : "0" ,
146- "PDN_TCL" : "$(PLATFORM_DIR)/openRoad/pdn/BLOCKS_grid_strategy.tcl" ,
147- "MACRO_HALO_X" : "0.5" ,
148- "MACRO_HALO_Y" : "0.5" ,
149- "MACRO_BLOCKAGE_HALO" : "0" ,
127+ "DIE_AREA" : "0 0 358.56 388.8" ,
128+ "CORE_AREA" : "2.16 2.16 356.40000000000003 386.64000000000004" ,
129+ "MACRO_PLACE_HALO" : "0 2.16" ,
130+ "RTLMP_BOUNDARY_WT" : "0" ,
131+ "PDN_TCL" : "$(PLATFORM_DIR)/openRoad/pdn/BLOCKS_grid_strategy.tcl" ,
132+ "MACRO_HALO_X" : "0.5" ,
133+ "MACRO_HALO_Y" : "0.5" ,
134+ "MACRO_BLOCKAGE_HALO" : "0" ,
150135 "ADDITIONAL_FILES" : "$(locations :mock-array-io)" ,
151136}
152137
@@ -162,12 +147,11 @@ orfs_flow(
162147 "place" : MOCK_ARRAY_FLOORPLAN_PLACE | {
163148 },
164149 "cts" : {
165- "CTS_BUF_DISTANCE" : "60"
150+ "CTS_BUF_DISTANCE" : "60" ,
166151 },
167152 "route" : {
168- "FASTROUTE_TCL" : "$(location :mock-array-fastroute)" ,
169153 # works with 28 or more iterations as of writing, so give it a few more.
170- "GLOBAL_ROUTE_ARGS" : "-congestion_iterations 40 -verbose" ,
154+ "GLOBAL_ROUTE_ARGS" : "-congestion_iterations 40 -verbose" ,
171155 # If this design isn't quickly done in detailed routing, something is wrong.
172156 # At time of adding this option, only 12 iterations were needed for 0
173157 # violations.
@@ -181,24 +165,22 @@ orfs_flow(
181165 "GDS_ALLOW_EMPTY" : "Element" ,
182166 "PWR_NETS_VOLTAGEsS" : "" ,
183167 "GND_NETS_VOLTAGES" : "" ,
184- }
168+ },
185169 },
186- verilog_files = glob (include = ["designs/src/mock-array/*.v" ]),
187170 stage_sources = {
188171 "synth" : all_sources + [":mock-array-constraints" ] + [":mock-array-io" ],
189172 "floorplan" : all_sources + [":mock-array-io" ],
190173 "place" : all_sources + [":mock-array-io" ],
191174 "cts" : all_sources ,
192- "route" : all_sources + [":mock-array-fastroute" ],
193175 "final" : all_sources ,
194176 },
177+ verilog_files = glob (include = ["designs/src/mock-array/*.v" ]),
195178)
196179
197-
198180filegroup (
199181 name = "mock-array-element-io" ,
200182 srcs = [
201- "designs/asap7/mock-array/Element/io.tcl"
183+ "designs/asap7/mock-array/Element/io.tcl" ,
202184 ],
203185 data = [
204186 "designs/src/mock-array/util.tcl" ,
@@ -208,20 +190,22 @@ filegroup(
208190
209191MOCK_ARRAY_ELEMENT_FLOORPLAN_PLACE = {
210192 "IO_CONSTRAINTS" : "$(location :mock-array-element-io)" ,
211- "PLACE_DENSITY" : "0.50" ,
212193 "PLACE_PINS_ARGS" : "-annealing" ,
213194}
214195
215196MOCK_ARRAY_ELEMENT_ALL = {
216- "MOCK_ARRAY_ROWS" : "8" ,
217- "MOCK_ARRAY_COLS" : "8" ,
197+ "MOCK_ARRAY_ROWS" : "8" ,
198+ "MOCK_ARRAY_COLS" : "8" ,
218199}
219200
220201mock_array_all_sources = ["designs/src/mock-array/util.tcl" ]
221202
222203orfs_flow (
223204 name = "Element" ,
224205 abstract_stage = "route" ,
206+ arguments = {
207+ "PLACE_DENSITY" : "0.82" ,
208+ },
225209 stage_arguments = {
226210 "synth" : MOCK_ARRAY_ELEMENT_ALL | {
227211 "SDC_FILE" : "$(location :mock-array-constraints)" ,
@@ -248,16 +232,27 @@ orfs_flow(
248232 "final" : MOCK_ARRAY_ELEMENT_ALL | {
249233 "PWR_NETS_VOLTAGES" : "" ,
250234 "GND_NETS_VOLTAGES" : "" ,
251- }
235+ },
252236 },
253- verilog_files = glob (include = ["designs/src/mock-array/*.v" ]),
254237 stage_sources = {
255238 "synth" : mock_array_all_sources + [":mock-array-constraints" ],
256239 "floorplan" : mock_array_all_sources + [":mock-array-element-io" ],
257240 "place" : mock_array_all_sources + [":mock-array-element-io" ],
258241 "cts" : mock_array_all_sources ,
259- "route" : mock_array_all_sources + [ ":mock-array-fastroute" ] ,
242+ "route" : mock_array_all_sources ,
260243 "final" : mock_array_all_sources ,
261244 },
245+ verilog_files = glob (include = ["designs/src/mock-array/*.v" ]),
262246)
263247
248+ filegroup (
249+ name = "ethmac_lvt_src" ,
250+ srcs = glob (include = ["designs/src/ethmac_lvt/*.v" ]),
251+ visibility = [":__subpackages__" ],
252+ )
253+
254+ compile_pip_requirements (
255+ name = "requirements" ,
256+ src = "util/requirements.in" ,
257+ requirements_txt = "util/requirements_lock.txt" ,
258+ )
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