Merge pull request #1117 from Pinata-Consulting/jake/mock-array-timing

mock-array-big: More detailed Element timing constraints

Author: maliberty

flow/designs/asap7/mock-array-big/Element/constraints.sdc

@@ -8,6 +8,8 @@ set clk_period 8000
 
 set clk_port [get_ports $clk_port_name]
 create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port
+set_clock_uncertainty -setup 20.0 [get_clocks $clk_name]
+set_clock_uncertainty -hold 20.0 [get_clocks $clk_name]
 
 # io_ins_x -> REG_x
 set_input_delay -clock $clk_name -min [expr $clk_period / 2] [get_ports {io_ins_*}]
@@ -38,3 +40,10 @@ set_output_delay -clock $clk_name -max $max_delay [get_ports {io_lsbOuts_7}]
 #  and do not need to be constrained.
 set non_clk_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
 set_false_path -from $non_clk_inputs -to [all_outputs]
+
+# Set driving cell and load capacitance explicitly to ensure timing results are sufficiently pessimistic
+set_driving_cell [all_inputs] -lib_cell BUFx2_ASAP7_75t_R
+# Assuming the load on each output is a BUFx2_ASAP7_75t_R, we pessimistically use 3 times the highest input
+#  pin capacitance for this cell, which is 0.577042.
+#  See platforms/asap7/lib/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz, line 1223.
+set_load -pin_load 1.731126 [all_outputs]