Merge pull request #2208 from Pinata-Consulting/rtlmp-fewer-surprises

maliberty · web-flow · commit bd25acc166b8 · 2024-07-31T10:20:27.000-07:00
makefile: RTLMP_FLOW is now more consistent, 1 if enabled and default empty
diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md
@@ -132,7 +132,7 @@ Note:
 | `FLOORPLAN_DEF`       | Use the DEF file to initialize floorplan.                                                                                                                                        |
 | `PLACE_SITE`          | Placement site for core cells defined in the technology LEF file.                                                                                                                |
 | `TAPCELL_TCL`         | Path to Endcap and Welltie cells file.                                                                                                                                           |
-| `RTLMP_FLOW`          | Enable the Hierarchical RTLMP flow. By default it is disabled.                                                                                                                   |
+| `RTLMP_FLOW`          | 1 to enable the Hierarchical RTLMP flow, default empty |
 | `MACRO_HALO`          | Specifies keep out distance from macro, in X and Y, to standard cell row.                                                                                                        |
 | `MACRO_PLACEMENT`     | Specifies the path of a file on how to place certain macros manually using read_macro_placement.                                                                                 |
 | `MACRO_PLACEMENT_TCL` | Specifies the path of a TCL file on how to place certain macros manually.                                                                                                        |
diff --git a/flow/Makefile b/flow/Makefile
@@ -657,7 +657,13 @@ endif
 
 # STEP 3: Timing Driven Mixed Sized Placement
 #-------------------------------------------------------------------------------
-ifeq ($(MACRO_PLACEMENT)$(MACRO_PLACEMENT_TCL)$(RTLMP_FLOW),)
+ifneq ($(MACRO_PLACEMENT)$(MACRO_PLACEMENT_TCL),)
+SKIP_TDMS:=1
+endif
+ifneq ($(RTLMP_FLOW), 1)
+SKIP_TDMS:=1
+endif
+ifneq ($(SKIP_TDMS), 1)
 $(eval $(call do-step,2_3_floorplan_tdms,$(RESULTS_DIR)/2_2_floorplan_io.odb $(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(LIB_FILES),tdms_place))
 else
 $(eval $(call do-copy,2_3_floorplan_tdms,2_2_floorplan_io.odb,$(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(LIB_FILES)))
diff --git a/flow/designs/asap7/aes-block/config.mk b/flow/designs/asap7/aes-block/config.mk
@@ -15,7 +15,7 @@ export PLACE_DENSITY          = 0.65
 
 export BLOCKS = aes_rcon aes_sbox
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 
 export PLACE_PINS_ARGS = -annealing
 export HAS_IO_CONSTRAINTS = 0
diff --git a/flow/designs/asap7/riscv32i/config.mk b/flow/designs/asap7/riscv32i/config.mk
@@ -3,7 +3,7 @@ export DESIGN_NAME = riscv_top
 export PLATFORM    = asap7
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 
 export RTLMP_MIN_INST = 1000
 export RTLMP_MAX_INST = 3500
diff --git a/flow/designs/asap7/swerv_wrapper/config.mk b/flow/designs/asap7/swerv_wrapper/config.mk
@@ -2,7 +2,7 @@ export DESIGN_NAME = swerv_wrapper
 export PLATFORM    = asap7
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
 export RTLMP_MIN_INST = 5000
diff --git a/flow/designs/gf12/ariane/config.mk b/flow/designs/gf12/ariane/config.mk
@@ -3,7 +3,7 @@ export PLATFORM    = gf12
 
 export SYNTH_HIERARCHICAL = 1
 export MAX_UNGROUP_SIZE ?= 10000
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 #
 
 export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/ariane.sv2v.v \
diff --git a/flow/designs/gf12/ariane133/config.mk b/flow/designs/gf12/ariane133/config.mk
@@ -4,7 +4,7 @@ export PLATFORM    = gf12
 
 export SYNTH_HIERARCHICAL = 1
 export MAX_UNGROUP_SIZE ?= 10000
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 #
 # RTL_MP Settings
 
diff --git a/flow/designs/gf12/bp_dual/config.mk b/flow/designs/gf12/bp_dual/config.mk
@@ -4,7 +4,7 @@ export PLATFORM    = gf12
 
 export SYNTH_HIERARCHICAL = 1
 #
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
 export RTLMP_MIN_INST = 10000
diff --git a/flow/designs/gf12/bp_quad/config.mk b/flow/designs/gf12/bp_quad/config.mk
@@ -2,7 +2,7 @@ export DESIGN_NICKNAME = bp_quad
 export DESIGN_NAME = bsg_chip
 export PLATFORM    = gf12
 
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 export SYNTH_HIERARCHICAL = 1
 export MAX_UNGROUP_SIZE ?= 1000
 
diff --git a/flow/designs/gf12/bp_single/config_mpl2.mk b/flow/designs/gf12/bp_single/config_mpl2.mk
@@ -6,7 +6,7 @@ export SKIP_GATE_CLONING = 1
 export TNS_END_PERCENT = 5
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 #
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/gf12/ca53/config.mk b/flow/designs/gf12/ca53/config.mk
@@ -1,7 +1,7 @@
 export DESIGN_NAME = ca53_cpu
 export PLATFORM    = gf12
 
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 
 export VERILOG_FILES  = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v
 export CACHED_NETLIST = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v
diff --git a/flow/designs/gf12/swerv_wrapper/config.mk b/flow/designs/gf12/swerv_wrapper/config.mk
@@ -3,7 +3,7 @@ export PLATFORM    = gf12
 #
 export MAX_UNGROUP_SIZE ?= 10000
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 
 # RTL_MP Settings
 export RTLMP_MAX_INST = 25000
diff --git a/flow/designs/gf12/tinyRocket/config.mk b/flow/designs/gf12/tinyRocket/config.mk
@@ -4,7 +4,7 @@ export PLATFORM    = gf12
 
 export SYNTH_HIERARCHICAL = 1
 export MAX_UNGROUP_SIZE ?= 1000
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 
 export VERILOG_FILES  = ./designs/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \
                         ./designs/src/$(DESIGN_NICKNAME)/ClockDivider2.v \
diff --git a/flow/designs/gf180/uart-blocks/config.mk b/flow/designs/gf180/uart-blocks/config.mk
@@ -7,7 +7,7 @@ export VERILOG_FILES = ./designs/src/uart-no-param/*.v
 export SDC_FILE      = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 export BLOCKS = uart_rx
 
 export DIE_AREA = 0 0 430 430
diff --git a/flow/designs/nangate45/ariane133/config.mk b/flow/designs/nangate45/ariane133/config.mk
@@ -3,7 +3,7 @@ export DESIGN_NICKNAME = ariane133
 export PLATFORM    = nangate45
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/nangate45/ariane136/config.mk b/flow/designs/nangate45/ariane136/config.mk
@@ -3,7 +3,7 @@ export DESIGN_NICKNAME = ariane136
 export PLATFORM    = nangate45
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/nangate45/black_parrot/config.mk b/flow/designs/nangate45/black_parrot/config.mk
@@ -3,7 +3,7 @@ export DESIGN_NAME = black_parrot
 export PLATFORM    = nangate45
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 #
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/nangate45/bp_be_top/config.mk b/flow/designs/nangate45/bp_be_top/config.mk
@@ -3,7 +3,7 @@ export DESIGN_NAME = bp_be_top
 export PLATFORM    = nangate45
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 #
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/nangate45/bp_fe_top/config.mk b/flow/designs/nangate45/bp_fe_top/config.mk
@@ -3,7 +3,7 @@ export DESIGN_NAME = bp_fe_top
 export PLATFORM    = nangate45
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 #
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/nangate45/bp_multi_top/config.mk b/flow/designs/nangate45/bp_multi_top/config.mk
@@ -3,7 +3,7 @@ export DESIGN_NAME = bp_multi_top
 export PLATFORM    = nangate45
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 #
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/nangate45/bp_quad/config.mk b/flow/designs/nangate45/bp_quad/config.mk
@@ -3,7 +3,7 @@ export DESIGN_NICKNAME = bp_quad
 export PLATFORM    = nangate45
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 
 # RTL_MP Settings
 #export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/nangate45/swerv_wrapper/config.mk b/flow/designs/nangate45/swerv_wrapper/config.mk
@@ -2,7 +2,7 @@ export DESIGN_NAME = swerv_wrapper
 export PLATFORM    = nangate45
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 #
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/nangate45/tinyRocket/config.mk b/flow/designs/nangate45/tinyRocket/config.mk
@@ -4,7 +4,7 @@ export PLATFORM    = nangate45
 
 export SYNTH_HIERARCHICAL = 1
 export MAX_UNGROUP_SIZE ?= 5000
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 
 export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \
                        ./designs/src/$(DESIGN_NICKNAME)/ClockDivider2.v \
diff --git a/flow/designs/sky130hd/coyote_tc/config.mk b/flow/designs/sky130hd/coyote_tc/config.mk
@@ -7,7 +7,7 @@ export PLATFORM    = sky130hd
 #
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 
 export SKY130_IO_VERSION ?= v0.2.0
 export OPENRAMS_DIR = ./platforms/sky130ram
diff --git a/flow/designs/sky130hd/microwatt/config.mk b/flow/designs/sky130hd/microwatt/config.mk
@@ -22,7 +22,7 @@ export ADDITIONAL_LEFS  = $(wildcard $(microwatt_DIR)/lef/*.lef)
 export ADDITIONAL_LIBS = $(wildcard $(microwatt_DIR)/lib/*.lib)
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 
 export RTLMP_BOUNDARY_WT = 0
 export MACRO_PLACE_HALO = 100 100
diff --git a/flow/designs/sky130hd_fakestack/ariane136/config.mk b/flow/designs/sky130hd_fakestack/ariane136/config.mk
@@ -4,7 +4,7 @@ export PLATFORM    = sky130hd_fakestack
 
 export SYNTH_HIERARCHICAL = 1
 export MAX_UNGROUP_SIZE = 10000
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 
 export SDC_FILE      = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 
diff --git a/flow/designs/tsmc65lp/ariane/config.mk b/flow/designs/tsmc65lp/ariane/config.mk
@@ -2,7 +2,7 @@ export DESIGN_NAME = ariane
 export PLATFORM    = tsmc65lp
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 
 export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/ariane.sv2v.v \
                        ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v
diff --git a/flow/designs/tsmc65lp/black_parrot/config.mk b/flow/designs/tsmc65lp/black_parrot/config.mk
@@ -3,7 +3,7 @@ export DESIGN_NAME = black_parrot
 export PLATFORM    = tsmc65lp
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 #
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/tsmc65lp/bp_be_top/config.mk b/flow/designs/tsmc65lp/bp_be_top/config.mk
@@ -3,7 +3,7 @@ export DESIGN_NAME = bp_be_top
 export PLATFORM    = tsmc65lp
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 #
 export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/pickled.v \
                        ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v
diff --git a/flow/designs/tsmc65lp/bp_fe_top/config.mk b/flow/designs/tsmc65lp/bp_fe_top/config.mk
@@ -3,7 +3,7 @@ export DESIGN_NAME = bp_fe_top
 export PLATFORM    = tsmc65lp
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 
 export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/pickled.v \
                        ./designs/$(PLATFORM)/$(DESIGN_NAME)/macros.v
diff --git a/flow/designs/tsmc65lp/bp_multi_top/config.mk b/flow/designs/tsmc65lp/bp_multi_top/config.mk
@@ -3,7 +3,7 @@ export DESIGN_NAME = bp_multi_top
 export PLATFORM    = tsmc65lp
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 #
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/tsmc65lp/coyote/config.mk b/flow/designs/tsmc65lp/coyote/config.mk
@@ -3,7 +3,7 @@ export DESIGN_NAME = bsg_rocket_node_client_rocc
 export PLATFORM    = tsmc65lp
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 
 
 # RTL_MP Settings
diff --git a/flow/designs/tsmc65lp/swerv_wrapper/config.mk b/flow/designs/tsmc65lp/swerv_wrapper/config.mk
@@ -2,7 +2,7 @@ export DESIGN_NAME = swerv_wrapper
 export PLATFORM    = tsmc65lp
 
 export SYNTH_HIERARCHICAL = 1
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 
 # RTL_MP Settings
 export RTLMP_MAX_INST = 30000
diff --git a/flow/designs/tsmc65lp/tinyRocket/config.mk b/flow/designs/tsmc65lp/tinyRocket/config.mk
@@ -4,7 +4,7 @@ export PLATFORM    = tsmc65lp
 
 export SYNTH_HIERARCHICAL = 1
 export MAX_UNGROUP_SIZE ?= 5000
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 
 export VERILOG_FILES = ./designs/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \
                        ./designs/src/$(DESIGN_NICKNAME)/ClockDivider2.v \
diff --git a/flow/designs/tsmc65lp/vanilla5/config.mk b/flow/designs/tsmc65lp/vanilla5/config.mk
@@ -17,7 +17,7 @@ export ADDITIONAL_GDS  = $(PLATFORM_DIR)/gds/tsmc65lp_1rf_lg10_w32_all.gds2 \
 
 export SYNTH_HIERARCHICAL = 1
 
-export RTLMP_FLOW = True
+export RTLMP_FLOW = 1
 
 # These values must be multiples of placement site
 export DIE_AREA    = 0 0 1100 400.8

Original file line number	Diff line number	Diff line change
`@@ -3,7 +3,7 @@ export PLATFORM = gf12`
`3`	`3`
`4`	`4`	`export SYNTH_HIERARCHICAL = 1`
`5`	`5`	`export MAX_UNGROUP_SIZE ?= 10000`
`6`		`-export RTLMP_FLOW = True`
	`6`	`+export RTLMP_FLOW = 1`
`7`	`7`	`#`
`8`	`8`
`9`	`9`	`export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/ariane.sv2v.v \`
Original file line number	Diff line number	Diff line change
`@@ -4,7 +4,7 @@ export PLATFORM = gf12`
`4`	`4`
`5`	`5`	`export SYNTH_HIERARCHICAL = 1`
`6`	`6`	`export MAX_UNGROUP_SIZE ?= 10000`
`7`		`-export RTLMP_FLOW = True`
	`7`	`+export RTLMP_FLOW = 1`
`8`	`8`	`#`
`9`	`9`	`# RTL_MP Settings`
`10`	`10`
Original file line number	Diff line number	Diff line change
`@@ -6,7 +6,7 @@ export SKIP_GATE_CLONING = 1`
`6`	`6`	`export TNS_END_PERCENT = 5`
`7`	`7`
`8`	`8`	`export SYNTH_HIERARCHICAL = 1`
`9`		`-export RTLMP_FLOW = True`
	`9`	`+export RTLMP_FLOW = 1`
`10`	`10`	`#`
`11`	`11`	`# RTL_MP Settings`
`12`	`12`	`export RTLMP_MAX_INST = 30000`