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2 parents 9d638a1 + f60577f commit be1e850Copy full SHA for be1e850
flow/designs/asap7/swerv_wrapper/constraint.sdc
@@ -3,7 +3,7 @@ current_design swerv_wrapper
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set clk_name core_clock
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set clk_port_name clk
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set clk_period 2500
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-set clk_io_pct 0.1
+set clk_io_pct 0.2
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set clk_port [get_ports $clk_port_name]
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