Merge pull request #729 from The-OpenROAD-Project-staging/clk_public

Clk public

Author: ravi-varadarajan

flow/designs/asap7/aes/constraint.sdc

@@ -1,6 +1,6 @@
 set clk_name  clk
 set clk_port_name clk
-set clk_period 500 
+set clk_period 400 
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]

flow/designs/asap7/aes/metadata-base-ok.json

@@ -32,19 +32,19 @@
         "compare": ">="
     },
     "cts__design__instance__count__setup_buffer": {
-        "value": 1105,
+        "value": 1449,
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
         "value": 1105,
         "compare": "<="
     },
     "globalroute__timing__clock__slack": {
-        "value": -35.7,
+        "value": -88.28,
         "compare": ">="
     },
     "globalroute__timing__setup__ws": {
-        "value": -35.7,
+        "value": -88.28,
         "compare": ">="
     },
     "detailedroute__route__wirelength": {
@@ -56,7 +56,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": 0.0,
+        "value": -46.35,
         "compare": ">="
     },
     "finish__design__instance__area": {

flow/designs/asap7/aes/rules-base.json

@@ -2,7 +2,7 @@ current_design gcd
 
 set clk_name  core_clock
 set clk_port_name clk
-set clk_period 400 
+set clk_period 390 
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]

flow/designs/asap7/gcd/constraint.sdc

@@ -20,7 +20,7 @@
         "compare": "=="
     },
     "cts__timing__setup__ws": {
-        "value": -150.09,
+        "value": -118.69,
         "compare": ">="
     },
     "cts__timing__setup__ws__pre_repair": {

flow/designs/asap7/gcd/metadata-base-ok.json

@@ -64,7 +64,7 @@
         "compare": "<="
     },
     "finish__timing__drv__max_slew_limit": {
-        "value": -1.40,
+        "value": -2.00,
         "compare": ">="
     },
     "finish__timing__drv__max_fanout_limit": {

flow/designs/asap7/gcd/rules-base.json

@@ -2,7 +2,7 @@ current_design ibex_core
 
 set clk_name  core_clock
 set clk_port_name clk_i
-set clk_period 3.5 
+set clk_period 2.8 
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]

flow/designs/nangate45/bp_multi_top/rules-base.json

@@ -12,7 +12,7 @@
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 17563,
+        "value": 17559,
         "compare": "<="
     },
     "detailedplace__design__violations": {
@@ -32,19 +32,19 @@
         "compare": ">="
     },
     "cts__design__instance__count__setup_buffer": {
-        "value": 764,
+        "value": 763,
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
-        "value": 764,
+        "value": 763,
         "compare": "<="
     },
     "globalroute__timing__clock__slack": {
-        "value": 0.0,
+        "value": -0.15,
         "compare": ">="
     },
     "globalroute__timing__setup__ws": {
-        "value": 0.0,
+        "value": -0.15,
         "compare": ">="
     },
     "detailedroute__route__wirelength": {
@@ -56,7 +56,7 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": 0.0,
+        "value": -0.18,
         "compare": ">="
     },
     "finish__design__instance__area": {