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Merge pull request #2547 from VidyaChhabria/master
Update config files to use DESIGN_HOME variable
2 parents 918b617 + ab25067 commit c01383b

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‎flow/designs/asap7/aes-block/config.mk‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,8 @@ export PLATFORM = asap7
33
export DESIGN_NAME = aes_cipher_top
44
export DESIGN_NICKNAME = aes-block
55

6-
export VERILOG_FILES = $(sort $(wildcard ./designs/src/aes/*.v))
7-
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
6+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/aes/*.v))
7+
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
88

99
export ABC_AREA = 1
1010

‎flow/designs/asap7/aes-mbff/config.mk‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,8 @@ export PLATFORM = asap7
33
export DESIGN_NAME = aes_cipher_top
44
export DESIGN_NICKNAME = aes-mbff
55

6-
export VERILOG_FILES = $(sort $(wildcard ./designs/src/aes/*.v))
7-
export SDC_FILE = ./designs/$(PLATFORM)/aes/constraint.sdc
6+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/aes/*.v))
7+
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/aes/constraint.sdc
88

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export ABC_AREA = 1
1010

‎flow/designs/asap7/aes/config.mk‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,8 @@ export PLATFORM = asap7
33
export DESIGN_NAME = aes_cipher_top
44
export DESIGN_NICKNAME = aes
55

6-
export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
7-
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
6+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
7+
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
88

99
export ABC_AREA = 1
1010

‎flow/designs/asap7/aes_lvt/config.mk‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,8 @@ export PLATFORM = asap7
33
export DESIGN_NAME = aes_cipher_top
44
export DESIGN_NICKNAME = aes_lvt
55

6-
export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
7-
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
6+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
7+
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
88

99
export ABC_AREA = 1
1010

‎flow/designs/asap7/ethmac/config.mk‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@ export PLATFORM = asap7
22

33
export DESIGN_NAME = ethmac
44

5-
export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
6-
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
5+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
6+
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
77
export ABC_AREA = 1
88

99
export CORE_UTILIZATION = 40

‎flow/designs/asap7/ethmac_lvt/config.mk‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,8 @@ export PLATFORM = asap7
33
export DESIGN_NAME = ethmac
44
export DESIGN_NICKNAME = ethmac_lvt
55

6-
export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
7-
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
6+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
7+
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
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export ABC_AREA = 1
99

1010
export CORE_UTILIZATION = 40

‎flow/designs/asap7/gcd/config.mk‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@ export PLATFORM = asap7
22

33
export DESIGN_NAME = gcd
44

5-
export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NAME)/*.v))
6-
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
5+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NAME)/*.v))
6+
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
77

88
export DIE_AREA = 0 0 16.2 16.2
99
export CORE_AREA = 1.08 1.08 15.12 15.12

‎flow/designs/asap7/ibex/config.mk‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,8 @@ export PLATFORM = asap7
33
export DESIGN_NICKNAME = ibex
44
export DESIGN_NAME = ibex_core
55

6-
export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
7-
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
6+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
7+
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
88

99
export CORE_UTILIZATION = 40
1010
export CORE_ASPECT_RATIO = 1

‎flow/designs/asap7/jpeg/config.mk‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@ export PLATFORM = asap7
33
export DESIGN_NAME = jpeg_encoder
44
export DESIGN_NICKNAME = jpeg
55

6-
export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
7-
export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include
8-
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc
6+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
7+
export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include
8+
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc
99
export ABC_AREA = 1
1010

1111
export CORE_UTILIZATION = 30

‎flow/designs/asap7/jpeg_lvt/config.mk‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@ export PLATFORM = asap7
33
export DESIGN_NAME = jpeg_encoder
44
export DESIGN_NICKNAME = jpeg_lvt
55

6-
export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
7-
export VERILOG_INCLUDE_DIRS = ./designs/src/$(DESIGN_NICKNAME)/include
8-
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc
6+
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
7+
export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/include
8+
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/jpeg_encoder15_7nm.sdc
99
export ABC_AREA = 1
1010

1111
export ADDITIONAL_LIBS = $(LIB_DIR)/asap7sc7p5t_AO_LVT_FF_nldm_211120.lib.gz \

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