Merge pull request #2768 from Pinata-Consulting/variables-add-yosys-flags

variables.yaml: add YOSYS_FLAGS

Author: maliberty

docs/user/FlowVariables.md

@@ -191,6 +191,7 @@ configuration file.
 | <a name="VERILOG_FILES"></a>VERILOG_FILES| The path to the design Verilog files or JSON files providing a description of modules (check `yosys -h write_json` for more details).| | |
 | <a name="VERILOG_INCLUDE_DIRS"></a>VERILOG_INCLUDE_DIRS| Specifies the include directories for the Verilog input files.| | |
 | <a name="VERILOG_TOP_PARAMS"></a>VERILOG_TOP_PARAMS| Apply toplevel params (if exist).| | |
+| <a name="YOSYS_FLAGS"></a>YOSYS_FLAGS| Additional flags to pass to yosys.| | |
 ## synth variables
 
 - [ABC_AREA](#ABC_AREA)
@@ -213,6 +214,7 @@ configuration file.
 - [VERILOG_FILES](#VERILOG_FILES)
 - [VERILOG_INCLUDE_DIRS](#VERILOG_INCLUDE_DIRS)
 - [VERILOG_TOP_PARAMS](#VERILOG_TOP_PARAMS)
+- [YOSYS_FLAGS](#YOSYS_FLAGS)
 
 ## floorplan variables
 

flow/scripts/variables.yaml

@@ -869,3 +869,8 @@ RUN_LOG_NAME_STEM:
     Stem of the log file name, the log file will be named
     `$(LOG_DIR)/$(RUN_LOG_NAME_STEM).log`.
   default: run
+YOSYS_FLAGS:
+  description: >
+    Additional flags to pass to yosys.
+  stages:
+    - synth